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| altera corporation 1 max 7000 programmable logic device family july 1999, ver. 6.01 data sheet a-ds-m7000-06.01 features... n high-performance, eeprom-based programmable logic devices (plds) based on second-generation multiple array matrix (max ) architecture n 5.0-v in-system programmability (isp) through the built-in ieee std. 1149.1 joint test action group (jtag) interface available in max 7000s devices n includes 5.0-v max 7000 devices and 5.0-v isp-based max 7000s devices n built-in jtag boundary-scan test (bst) circuitry in max 7000s devices with 128 or more macrocells n complete epld family with logic densities ranging from 600 to 5,000 usable gates (see tables 1 and 2 ) n 5-ns pin-to-pin logic delays with up to 175.4-mhz counter frequencies (including interconnect) n peripheral component interconnect (pci)-compliant devices available f for information on in-system programmable 3.3-v max 7000a or 2.5-v max 7000b devices, see the max 7000a programmable logic device family data sheet or the max 7000b programmable logic devices advance information brief . table 1. max 7000 device features feature epm7032 epm7064 epm7096 epm7128e epm7160e epm7192e epm7256e usable gates 600 1,250 1,800 2,500 3,200 3,750 5,000 macrocells 32 64 96 128 160 192 256 logic array blocks 2 4 6 8 101216 maximum user i/o pins 36 68 76 100 104 124 164 t pd (ns) 6 6 7.5 7.5 10 12 12 t su (ns) 5 5 66777 t fsu (ns) 2.5 2.5 33333 t co1 (ns) 4 4 4.5 4.5 5 6 6 f cnt (mhz) 151.5 151.5 125.0 125.0 100.0 90.9 90.9 includes max 7000e & max 7000s
2 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet ...and more features n open-drain output option in max 7000s devices n programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls n programmable power-saving mode for a re duction of over 50 % in each macrocell n configurable expander product-term distribution, allowing up to 3 2 product terms per macrocell n 44 to 208 pins available in plastic j-lead chip carrier (plcc), ceramic pin-grid array (pga), plastic quad flat pack (pqfp), power quad flat pack (rqfp), and 1.0-mm thin quad flat pack (tqfp) packages n programmable securi ty bit for protection of proprietary designs n 3.3-v or 5.0-v operation multivolt tm i/o interface operation, allowing devices to interface with 3.3-v or 5.0-v devices (multivolt i/o operation is not available in 44-pin packages) pin compatible with low-voltage max 7000a and max 7000b devices n enhanced features available in max 7000e and max 7000s devices six pin- or logic-driven output enable signals two global clock signals with optional inversion enhanced interconnect resources for improved routability fast input setup times provided by a dedicated path from i/o pin to macrocell registers programmable output slew-rate control n software design support and automatic place-and-route provided by altera? max+p l us i i development system for windows-based pcs and sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations , and the quartus tm development system for windows-based pcs and sun sparcstation and hp 9000 series 700 workstations table 2. max 7000s device features feature epm7032s epm7064s epm7128s epm 7160s epm 7192s epm 7256s usable gates 600 1,250 2,500 3,200 3,750 5,000 macrocells 32 64 128 160 192 256 logic array blocks 2 4 8 10 12 16 maximum user i/o pins 36 68 100 104 124 164 t pd (ns) 5 5 6 6 7.5 7.5 t su (ns) 2.9 2.9 3.4 3.4 4.1 3.9 t fsu (ns) 2.5 2.5 2.5 2.5 3 3 t co1 (ns) 3.2 3.2 4 3.9 4.7 4.7 f cnt (mhz) 175.4 175.4 147.1 149.3 125.0 128.2 altera corporation 3 max 7000 pr ogrammab le logic de vice f amil y data sheet n additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, library of parameterized modules (lpm), verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, and veribest n programming support altera? master programming unit (mpu) and programming hardware from third-party manufacturers program all max 7000 devices the bitblaster tm serial download cable, byteblaster tm parallel port download cable, byteblastermv tm parallel port download cable, and masterblaster tm serial/universal serial bus (usb) download cable program max 7000s devices general description the max 7000 family of high-density, high-performance p lds i s based on altera? second-generation max architecture. fabricated with advanced cmos technology, the eeprom-based max 7000 family provides 600 to 5,000 usable gates, isp, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 mhz. max 7000s devices in the - 5, - 6, - 7, and - 10 speed grades as well as max 7000 and max 7000e devices in - 5, - 6, - 7, - 10p, and - 12p speed grades comply with the pci special interest group (pci sig) p ci local bu s specification , revision 2.2 . see table 3 for available speed grades. table 3. max 7000 s peed grades device speed grade -5 -6 -7 -10p -10 -12p -12 -15 -15t -20 epm7032 v v v v v v epm7032s v v v v epm7064 v v v v v epm7064s v v v v epm7096 v v v v epm7128e v v v v v v epm7128s v v v v epm7160e v v v v v epm7160s v v v v epm7192e v v v v epm7192s v v v epm7256e v v v v epm7256s v v v 4 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet the max 7000e devices?ncluding the epm7128e, epm7160e, epm7192e, and epm7256e devices?ave several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate. in-system programmable max 7000 devices?alled max 7000s devices?nclude the epm7032s, epm7064s, epm7128s, epm7160s, epm7192s, and epm7256s devices. max 7000s devices have the enhanced features of max 7000e devices as well as jtag bst circuitry in devices with 128 or more macrocells, isp, and an open-drain output option. see table 4 . notes: (1) available in epm7128s, epm7160s, epm7192s, and epm7256s devices only. (2) the multivolt i/o interface is not available in 44-pin packages. table 4. max 7000 device features feature epm7032 epm7064 epm7096 all max 7000e devices all max 7000s devices isp via jtag interface v jtag bst circuitry v (1) open-drain output option v fast input registers v v six global output enables v v two global clocks v v slew-rate control v v multivolt interface (2) v v v programmable register v v v parallel expanders v v v shared expanders v v v power-saving mode v v v security bit v v v pci-compliant devices available v v v altera corporation 5 max 7000 pr ogrammab le logic de vice f amil y data sheet the max 7000 architecture supports 100 % ttl emulation and high- density integration of ssi, msi, and lsi logic functions. it easily integrates multiple devices ranging from pals, gals, and 22v10s to mach and plsi d evices. m ax 7000 devices are available in a wide range of packages, including plcc, pga, pqfp, rqfp, and tqfp packages. see table 5 . notes: (1) when the jtag interface in max 7000s devices is used, four i/o pins become jtag pins. (2) perform a complete thermal analysis before committing a design to this device package. see the operating requirements for altera devices data sheet for more information. max 7000 devices use cmos eeprom cells to implement logic functions. the user-configurable max 7000 architecture accommodates a variety of independent combinatorial and sequential logic functions. the devices can be reprogrammed for quick and efficient iterations during design development and debug cycles, and can be programmed and erased up to 100 times. table 5. max 7000 maxim um user i/o pins note (1) device 44- pin plcc 44- pin pqfp 44- pin tqfp 68- pin plcc 84- pin plcc 100- pi n pqfp 100- pin tqfp 160- pin pqfp 160- pin pga 192- pin pga 208- pin pqfp 208- pin rqfp epm7032 36 36 36 epm7032s 36 36 epm7064 36 36 52 68 68 epm7064s 36 36 68 68 epm7096 52 64 76 epm7128e 68 84 100 epm7128s 68 84 84 (2) 100 epm7160e 64 84 104 epm7160s 64 84 (2) 104 epm7192e 124 124 epm7192s 124 epm7256e 132 (2) 164 164 epm7256s 164 (2) 164 6 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet max 7000 devices contain from 32 to 256 macrocells that are combined into groups of 16 macrocells, called logic array blocks (labs). each macrocell has a programmable- and /fixed- or array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. to build complex logic functions, each macrocell can be supplemented with both shareable expander product terms and high-speed parallel expander product terms to provide up to 32 product terms per macrocell. the max 7000 family provides programmable speed/power optimization. speed-critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. this speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50 % or lower power while adding only a nominal timing delay. m ax 7000e and max 7000s devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non-speed-critical signals are switching. the output drivers of all max 7000 devices (except 44-pin devices) can be set for either 3.3-v or 5.0-v operation, allowing max 7000 devices to be used in mixed-voltage systems. the max 7000 family is supported by the quartus and max+plus ii development systems, a single, integrated package that allows schematic, text?ncluding vhdl, verilog hdl, and the altera hardware description language (ahdl)?nd waveform design entry , c ompilation and logic synthesis , s imulation and timing analysis, and device programming. the quartus and max+plus ii software provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry-standard pc- and unix-workstation- based eda tools. the max+plus ii software runs on windows- based pcs, as well as sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations. the quartus software runs on windows-based pcs, as well as sun sparcstation and hp 9000 series 700 workstations . f for more information on development tools, go to the max+plus ii programmable logic development system & software data sheet . funct ional description the max 7000 architecture includes the following elements: n logic array blocks n macrocells n expander product terms (shareable and parallel) n programmable interconnect array n i/o control blocks altera corporation 7 max 7000 pr ogrammab le logic de vice f amil y data sheet the max 7000 architecture includes four dedicated inputs that can be used as general-purpose inputs or as high-speed, global control signals (clock, clear, and two output enable signals) for each macrocell and i/o pin. figure 1 shows the architecture of epm7032, epm7064, and epm7096 devices. figure 1. epm7032, epm7064 & epm7096 device block diagram i / o c o n t r o l b l o c k 8 t o 1 6 i / o p i n s 8 t o 1 6 8 t o 1 6 1 6 3 6 i / o c o n t r o l b l o c k 8 t o 1 6 8 t o 1 6 i / o p i n s 3 6 8 t o 1 6 1 6 8 t o 1 6 8 t o 1 6 i / o p i n s 3 6 8 t o 1 6 1 6 i / o c o n t r o l b l o c k i / o c o n t r o l b l o c k 8 t o 1 6 i / o p i n s 8 t o 1 6 8 t o 1 6 1 6 3 6 l a b a l a b b l a b c m a c r o c e l l s 3 3 t o 4 8 l a b d i n p u t / g c l r n i n p u t / o e 1 n i n p u t / o e 2 n m a c r o c e l l s 1 7 t o 3 2 m a c r o c e l l s 4 9 t o 6 4 p i a i n p u t / g l c k 1 m a c r o c e l l s 1 t o 1 6 8 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet figure 2 shows the architecture of max 7000e and max 7000s devices. figure 2. max 7000e & max 7000s device block diagram logic arra y blocks the max 7000 device architecture is based on the linking of high- performance, flexible, logic array modules called logic array blocks (labs). labs consist of 16-macrocell arrays, as shown in figures 1 and 2 . multiple labs are linked together via the programmable interconnect array (pia), a global bus that is fed by all dedicated inputs, i/o pins, and macrocells. 6 6 i n p u t / g c l r n 6 o u t p u t e n a b l e s 6 o u t p u t e n a b l e s 1 6 3 6 3 6 1 6 i / o c o n t r o l b l o c k l a b c l a b d i / o c o n t r o l b l o c k 6 1 6 3 6 3 6 1 6 i / o c o n t r o l b l o c k l a b a l a b b i / o c o n t r o l b l o c k 6 6 t o 1 6 i n p u t / g c l k 1 i n p u t / o e 2 / g c l k 2 i n p u t / o e 1 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 i / o p i n s 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 6 t o 1 6 m a c r o c e l l s 1 t o 1 6 m a c r o c e l l s 1 7 t o 3 2 m a c r o c e l l s 3 3 t o 4 8 m a c r o c e l l s 4 9 t o 6 4 p i a altera corporation 9 max 7000 pr ogrammab le logic de vice f amil y data sheet each lab is fed by the following signals: n 36 signals from the p ia t hat are used for general logic inputs n global controls that are used for secondary register functions n direct input paths from i/o pins to the registers that are used for fast setup times for max 7000e and max 7000s devices macrocells the max 7000 macrocell can be individually configured for either sequential or combinatorial logic operation. the macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register. the macrocell of epm7032, epm7064, and epm7096 devices is shown in figure 3 . figure 3. epm7032, epm7064 & epm7096 device macrocell p r o d u c t - t e r m s e l e c t m a t r i x 3 6 s i g n a l s f r o m p i a 1 6 e x p a n d e r p r o d u c t t e r m s l o g i c a r r a y p a r a l l e l l o g i c e x p a n d e r s ( f r o m o t h e r m a c r o c e l l s ) s h a r e d l o g i c e x p a n d e r s c l e a r s e l e c t p r n c l r n d / t q g l o b a l c l e a r g l o b a l c l o c k c l o c k / e n a b l e s e l e c t e n a r e g i s t e r b y p a s s t o i / o c o n t r o l b l o c k t o p i a p r o g r a m m a b l e r e g i s t e r v c c 10 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet t he macrocell of max 7000e and max 7000s devices is shown in figure 4 . figure 4. max 7000e & max 7000s device macrocell combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. the product-term select matrix allocates these product terms for use as either primary logic inputs (to the or and xor gates) to implement combinatorial functions, or as secondary inputs to the macrocell? register clear, preset, clock, and clock enable control functions. two kinds of expander product terms (?xpanders? are available to supplement macrocell logic resources: n shareable expanders, which are inverted product terms that are fed back into the logic array n parallel expanders, which are product terms borrowed from adjacent macrocells the quartus and max+plus ii software automatically optimizes product-term allocation according to the logic requirements of the design. for registered functions, each macrocell flipflop can be individually programmed to implement d, t, jk, or sr operation with programmable clock control. the flipflop can be bypassed for combinatorial operation. during design entry, the designer specifies the desired flipflop type; the quartus and max+plus ii software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. p r o d u c t - t e r m s e l e c t m a t r i x 3 6 s i g n a l s f r o m p i a 1 6 e x p a n d e r p r o d u c t t e r m s l o g i c a r r a y p a r a l l e l l o g i c e x p a n d e r s ( f r o m o t h e r m a c r o c e l l s ) s h a r e d l o g i c e x p a n d e r s c l e a r s e l e c t g l o b a l c l e a r g l o b a l c l o c k s c l o c k / e n a b l e s e l e c t 2 p r n c l r n d / t q e n a r e g i s t e r b y p a s s t o i / o c o n t r o l b l o c k t o p i a p r o g r a m m a b l e r e g i s t e r f r o m i / o p i n f a s t i n p u t s e l e c t v c c altera corporation 11 max 7000 pr ogrammab le logic de vice f amil y data sheet each programmable register can be clocked in three different modes: n by a global clock signal. this mode achieves the fastest clock-to- output performance. n by a global clock signal and enabled by an active-high clock enable. this mode provides an enable on each flipflop while still achieving the fast clock-to-output performance of the global clock. n by an array clock implemented with a product term. in this mode, the flipflop can be clocked by signals from buried macrocells or i/o pins. in epm7032, epm7064, and epm7096 devices, the global clock signal is available from a dedicated clock pin, gclk1 , as shown in figure 1 . in max 7000e and max 7000s devices, two global clock signals are available. as shown in figure 2 , these global clock signals can be the true or the complement of either of the global clock pins, gclk1 or gclk2 . each register also supports asynchronous preset and clear functions. as shown in figures 3 and 4 , the product-term select matrix allocates product terms to control these operations. although the product- term-driven preset and clear of the register are active high, active- low control can be obtained by inverting the signal within the logic array. in addition, each register clear function can be individually driven by the active-low dedicated global clear pin ( gclrn ). all max 7000e and max 7000s i/o pins have a fast input path to a macrocell register. this dedicated path allows a signal to bypass the pia and combinatorial logic and be driven to an input d flipflop with an extremely fast ( 2.5- ns) input setup time. expander product t erms although most logic functions can be implemented with the five product terms available in each macrocell, the more complex logic functions require additional product terms. another macrocell can be used to supply the required logic resources; however, the m ax 7000 architecture also allows both shareable and parallel expander product terms (?xpanders? that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. 12 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet shareable expanders each lab has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. each shareable expander can be used and shared by any or all macrocells in the lab to build complex logic functions. a small delay ( t sexp ) is incurred when shareable expanders are used. figure 5 shows how shareable expanders can feed multiple macrocells. figure 5. shareable expanders shareable expanders can be shared by any or all macrocells in an lab. parallel expanders parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. parallel expanders allow up to 20 product terms to directly feed the macrocell or logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the lab. macrocell product-t erm logic product-t erm select matrix macrocell product-t erm logic 36 signals from pia 16 shared expanders altera corporation 13 max 7000 pr ogrammab le logic de vice f amil y data sheet the quartus and max+plus ii compilers can allocate up to three sets of up to five parallel expanders automatically to the macrocells that require additional product terms. each set of five parallel expanders incurs a small, incremental timing delay ( t pexp ). for example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms and the second set includes 4 product terms, increasing the total delay by 2 t pexp . two groups of 8 macrocells within each lab (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. a macrocell borrows parallel expanders from lower-numbered macrocells. for example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. within each group of 8, the lowest- numbered macrocell can only lend parallel expanders and the highest-numbered macrocell can only borrow them. figure 6 shows how parallel expanders can be borrowed from a neighboring macrocell. figure 6. parallel expanders unused product terms in a macrocell can be allocated to a neighboring macrocell. p r e s e t c l o c k c l e a r p r o d u c t - t e r m s e l e c t m a t r i x p r e s e t c l o c k c l e a r p r o d u c t - t e r m s e l e c t m a t r i x m a c r o c e l l p r o d u c t - t e r m l o g i c f r o m p r e v i o u s m a c r o c e l l t o n e x t m a c r o c e l l m a c r o c e l l p r o d u c t - t e r m l o g i c 3 6 s i g n a l s f r o m p i a 1 6 s h a r e d e x p a n d e r s 14 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet p rogra mmable interconnect array logic is routed between labs via the programmable interconnect array (pia). this global bus is a programmable path that connects any signal source to any destination on the device. all max 7000 dedicated inputs, i/o pins, and macrocell outputs feed the pia, which makes the signals available throughout the entire device. only the signals required by each lab are actually routed from the pia into the lab. figure 7 shows how the pia signals are routed into the lab. an eeprom cell controls one input to a 2- input and gate, which selects a pia signal to drive into the lab. figure 7. pia routing while the routing delays of channel-based routing schemes in masked or field-programmable gate arrays (fpgas) are cumulative, variable, and path-dependent, the max 7000 pia has a fixed delay. the pia thus eliminates skew between signals and makes timing performance easy to predict. i/o co ntrol blocks the i/o control block allows each i/o pin to be individually configured for input, output, or bidirectional operation. all i/o pins have a tri-state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or v cc . figure 8 shows the i/o control block for the max 7000 family. the i/o control block of epm7032, epm7064, and epm7096 devices has two global output enable signals that are driven by two dedicated active- low output enable pins ( oe1 and oe2 ). the i/o control block of max 7000e and max 7000s devices has six global output enable signals that are driven by the true or complement of two output enable signals, a subset of the i/o pins, or a subset of the i/o macrocells. to lab pia signals altera corporation 15 max 7000 p r ogrammable logic d e vice f ami l y data sheet figure 8. i/o control blo ck of max 7000 devices note: (1) the open-drain output option is available in max 7000s devices only. epm7032, epm7064 & epm7096 devices max 7000e & max 7000s devices t o p i a g n d v c c f r o m m a c r o c e l l o e 1 o e 2 f r o m m a c r o c e l l f a s t i n p u t t o m a c r o c e l l r e g i s t e r s l e w - r a t e c o n t r o l t o p i a t o o t h e r i / o p i n s s i x g l o b a l o u t p u t e n a b l e s i g n a l s p i a g n d v c c o p e n - d r a i n o u t p u t ( 1 ) 16 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet when the tri-state buffer control is connected to ground , the output i s t ri-stated (high impedance) and the i/o pin can be used as a dedicated input. when the tri-state buffer control is connected to v cc , the output is enabled. the max 7000 architecture provides dual i/o feedback, in which macrocell and pin feedbacks are independent. when an i/o pin is configured as an input, the associated macrocell can be used for buried logic. in-system prog ramma- bility (isp) max 7000s devices are in-system programmable via an industry- standard 4-pin joint test action group (jtag) interface (ieee std. 1149.1- 1990). isp allows quick, efficient iterations during design development and debugging cycles. the max 7000s architecture internally generates the high programming voltage required to program eeprom cells, allowing in-system programming with only a single 5.0 v power supply. during in-system programming, the i/o pins are tri-stated and pulled-up to eliminate board conflicts. the pull-up value is nominally 50 k w . isp simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board with standard in-circuit test equipment before they are programmed. max 7000s devices can be programmed by downloading the information via in-circuit testers (ict), embedded processors, or the altera bitb laster, byte blaster, b ytebl astermv , or masterblaster d ownload cables. (the byteblaster cable is obsolete and is replaced by the byteblastermv cable, which can program and configure 2.5-v, 3.3-v, and 5.0-v devices.) p rogramming the devices after they are placed on the board eliminates lead damage on high-pin-count packages (e.g., qfp packages) due to device handling and allows d evices to b e reprogrammed after a system has already shipped to the field. for example, product upgrades can be performed in the field via software or modem. in-system programming can be accomplished with either an adaptive or constant algorithm. an adaptive algorithm reads information from the unit and adapts subsequent programming steps to achieve the fastest possible programming time for that unit. because some in-circuit testers can not support a n adaptive algorithm, altera offers devices tested with a constant algorithm. devices tested to the constant algorithm are marked with an ??suffix in the ordering code. the jam tm programming and t est l anguage can be used to program max 7000s devices with in-circuit test equipment (e.g., pc, embedded processor). f for more information on using the jam language, see application note 88 (using the jam language for isp & icr via an embedded processor) . altera corporation 17 max 7000 pr ogrammab le logic de vice f amil y data sheet progr ammable speed/power control max 7000 devices offer a power-saving mode that supports low-power operation across user-defined signal paths or the entire device. this feature allows total power dissipation to be reduced by 50 % or more, because most logic applications require only a small fraction of all gates to operate at maximum frequency. the designer can program each individual macrocell in a max 7000 device for either high-speed ( i.e., with the turbo bit tm option turned on) or low-power (i.e., with the turbo bit option turned off) operation. as a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. macrocells that run at low power incur a nominal timing delay adder ( t lpa ) for the t lad , t lac , t ic , t en , and t sexp , t acl , and t cppw parameters. output con gu ration max 7000 device outputs can be programmed to meet a variety of system-level requirements. mult iv olt i/o interface max 7000 devices ? xcept 44-pin devices ? upport the multivolt i /o interface feature , w hich allows max 7000 devices to interface with systems that have differing supply voltages. the 5.0-v devices in all packages can be set for 3.3-v or 5.0-v i/o pin operation. these devices have one set of v cc pins for internal operation and input buffers ( v ccint ), and another set for i/o output drivers ( v ccio ). the v ccint pins must always be connected to a 5.0-v power supply. with a 5.0-v v ccint level, input voltage thresholds are at ttl levels, and are therefore compatible with both 3.3-v and 5.0-v i nputs. the v ccio pins can be connected to either a 3.3-v or a 5.0-v power supply, depending on the output requirements. when the v ccio pins are connected to a 5.0-v supply, the output levels are compatible with 5.0-v systems. when v ccio is connected to a 3.3-v supply, the output high is 3.3 v and is therefore compatible with 3.3-v or 5.0- v systems. devices operating with v ccio levels lower than 4.75 v incur a nominally greater timing delay of t od2 instead of t od1 . open-dr ain output option (max 7000s devices only) max 7000s devices provide an optional open-drain (functionally equivalent to open-collector) output for each i/o pin. this open-drain output enables the device to provide system-level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. it can also provide an additional wired- or plane. 18 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet output pins on 5.0-v max 7000s devices with v ccio = 3.3 v or 5.0 v (with a pull-up resistor to the 5.0- v supply) can also drive 5.0-v cmos input pins. in this case, the pull-up transistor will turn off when the pin voltage exceeds 3.3 v. therefore, the pin does not have to be open-drain. slew-r ate control the output buffer for each max 7000e and max 7000s i/o pin has an adjustable output slew rate that can be configured for low-noise or high- speed performance. a faster slew rate provides high-speed transitions for high-performance systems. however, these fast transitions may introduce noise transients into the system. a slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. in max 7000e devices, when the turbo bit is turned off, the slew rate is set for low noise performance. for max 7000s devices, each i/o pin has an individual eeprom bit that controls the slew rate, allowing designers to specify the slew rate on a pin- by-pin basis. program ming with external hardware max 7000 devices can be programmed on windows-based pcs with the max+plus ii programmer, an altera logic programmer card, the master programming unit (mpu), and the appropriate device adapter. the mpu performs a continuity check t o ensure adequate electrical contact between the adapter and the device. for more information, see the altera programming hardware data sheet . the max+plus ii software can use text- or waveform-format test vectors created with the max+plus ii text editor or waveform editor to test the programmed device. for added design verification, designers can perform functional testing to compare the functional behavior of a max 7000 device with the results of simulation. moreover, data i/o, bp microsystems, and other programming hardware manufacturers also provide programming support for altera devices. for more information, see programming hardware manufacturers . altera corporation 19 max 7000 pr ogrammab le logic de vice f amil y data sheet ieee std. 1 149.1 (jt ag) boundar y-scan support max 7000 devices support jtag bst circuitry as specified by ieee std. 1149.1-1990. table 6 describes the jtag instructions supported by the max 7000 family. the pin-out tables starting on page 55 of this data sheet show the location of the jtag control pins for each device. if the jtag interface is not required, the jtag pins are available as user i/o pins. table 6. max 7000 jtag instructions jtag instruction devices description sample/prelo ad epm7128s epm7160s epm7192s epm7256s allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins. extest epm7128s epm7160s epm7192s epm7256s allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. byp ass epm7032s epm7064s epm7128s epm7160s epm7192s epm7256s places the 1-bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through a selected device to adjacent devices during normal device operation. idcode epm7032s epm7064s epm7128s epm7160s epm7192s epm7256s selects the idcode register and places it between tdi and tdo , allowing the idcode to be serially shifted out of tdo . isp instr uctions epm7032s epm7064s epm7128s epm7160s epm7192s epm7256s these instructions are used when programming max 7000s devices via the jtag ports with the bitblaster, byteblaster, byteblastermv, or masterblaster download cable, or using a jam file ( .jam ) , jam byte- code ( .jbc ) , or s erial vector format ( .svf ) file via an embedded processor or test equipment. 20 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet the instruction register length of max 7000s devices is 10 bits. tables 7 and 8 show the boundary-scan register length and device idcode information for max 7000s devices. note: (1) this device does not support jtag boundary-scan testing . note s : (1) the most significant bit (msb) is on the left. (2) the least significant bit (lsb) for all jtag idcodes is 1 . table 7. max 7000s boundary-scan register length device boundary-scan register length ep m 7032s 1 (1) ep m 7064s 1 (1) ep m 7128s 288 ep m 7160s 312 ep m 7192s 360 ep m 7256s 480 table 8. 32-bit max 7000 device idcode note (1) device idcode (32 bits) version (4 bits) part number (16 bits) manufacturer? identity (11 bits) 1 (1 bit) (2) ep m 7032s 0000 0111 0000 0011 0010 00001101110 1 ep m 7064s 0000 0111 0000 0110 0100 00001101110 1 ep m 7128s 0000 0111 0001 0010 1000 00001101110 1 ep m 7160s 0000 0111 0001 0110 0000 00001101110 1 ep m 7192s 0000 0111 0001 1001 0010 00001101110 1 ep m 7256s 0000 0111 0010 0101 0110 00001101110 1 altera corporation 21 max 7000 pr ogrammab le logic de vice f amil y data sheet figure 9 shows the timing requirements for the jtag signals. figure 9. max 7000 jt ag w aveforms table 9 shows the jtag timing parameters and values for max 7000s devices. f for more information, see application note 39 (ieee 1149.1 (jtag) boundary-scan testing in altera devices) . table 9. jtag timing parameters & values for max 7000s devices symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns t d o t c k t j p z x t j p c o t j p h t j p x z t j c p t j p s u t j c l t j c h t d i t m s s i g n a l t o b e c a p t u r e d s i g n a l t o b e d r i v e n t j s z x t j s s u t j s h t j s c o t j s x z 22 altera corporation max 7000 p r ogrammable logic d e vice f ami l y data sheet design security all max 7000 devices contain a programmable security bit that controls access to the data programmed into the device. when this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security, because programmed data within eeprom cells is invisible. the security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. generic t esting each max 7000 device is functionally tested. complete testing of each programmable eeprom bit and all internal logic elements ensures 10 0 % programming yield. ac test measurements are taken under conditions equivalent to those shown in figur e 10 . test patterns can be used and then erased during early stages of the production flow. figure 10. max 7000 ac test conditions qfp carrier & development socket max 7000 and max 7000e devices in qfp packages with 100 or more pins are shipped in special plastic carriers to protect the qfp leads. the carrier is used with a prototype development socket and special programming hardware available from altera. this carrier technology makes it possible to program, test, erase, and reprogram a device without exposing the leads to mechanical stress. f for detailed information and carrier dimensions, refer to th e qfp carrier & development socket data sheet . 1 max 7000s devices are not shipped in carriers. v c c t o t e s t s y s t e m c 1 ( i n c l u d e s j i g c a p a c i t a n c e ) d e v i c e i n p u t r i s e a n d f a l l t i m e s < 3 n s d e v i c e o u t p u t 4 6 4 w [ 7 0 3 w ] 2 5 0 [ 8 . 0 6 ] w k w power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large-amplitude, fast ground-current transients normally occur as the device outputs discharge the load capacitances. when these transients ow through the parasitic inductance between the device ground pin and the test system ground, signi cant reductions in observable noise immuni t y can result. numbers in brackets are for 2.5-v devices and outputs. numbers without brackets are for 3.3-v devices and outputs. altera corporation 23 max 7000 p r ogrammable logic d e vice f ami l y data sheet operating conditions tables 10 through 15 provide information about absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-v max 7000 devices. table 10. max 7000 5.0-v device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) ?.0 7.0 v v i dc input voltage ?.0 7.0 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 150 ?c t amb ambient temperature under bias ? 5 135 ?c t j junction temperature ceramic packages, under bias 150 ?c pqfp and rqfp packages, under bias 135 ?c table 11. max 7000 5.0-v device recommended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (3) , (4) 4.75 (4.50) 5.25 (5.50) v v ccio supply voltage for output drivers, 5.0-v operation (3) , (4) 4.75 (4.50) 5.25 (5.50) v supply voltage for output drivers, 3.3-v operation (3) , (4) , (5) 3.00 (3.00) 3.60 (3.60) v v ccisp supply voltage during isp (6) 4.75 5.25 v v i input voltage ?.5 (7) v ccint + 0.5 v v o output voltage 0 v ccio v t a ambient temperature for commercial use 0 70 ?c for industrial use ?0 85 ?c t j junction temperature for commercial use 0 90 ?c for industrial use ?0 105 ?c t r input rise time 40 ns t f input fall time 40 ns 24 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 12. max 7000 5.0-v device dc operating conditions note (8) symbol parameter conditions min max unit v ih high-level input voltage 2.0 v ccint + 0.5 v v il low-level input voltage ?.5 (7) 0.8 v v oh 5.0-v high-level ttl output voltage i oh = ? ma dc, v ccio = 4.75 v (9) 2.4 v 3.3-v high-level ttl output voltage i oh = ? ma dc, v ccio = 3.00 v (9) 2.4 v 3.3-v high-level cmos output voltage i oh = ?.1 ma dc, v ccio = 3.0 v (9) v ccio ?0.2 v v ol 5.0-v low-level ttl output voltage i ol = 12 ma dc, v ccio = 4.75 v (10) 0.45 v 3.3-v low-level ttl output voltage i ol = 12 ma dc, v ccio = 3.00 v (10) 0.45 v 3.3-v low-level cmos output voltage i ol = 0.1 ma dc, v ccio = 3.0 v (10) 0.2 v i i leakage current of dedicated input pins v i = v cc or ground ?0 10 ? i oz i/o pin tri-state output off-state current v o = v cc or ground (11) ?0 40 ? table 13. max 7000 5.0-v device capacitance: epm7032, epm7064 & epm7096 devices note (12) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 12 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 12 pf table 14. max 7000 5.0-v device capacitance: max 7000e devices note (12) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 15 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 15 pf table 15. max 7000 5.0-v device capacitance: max 7000s devices note (12) symbol parameter conditions min max unit c in dedicated input pin capacitance v in = 0 v, f = 1.0 mhz 10 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 10 pf altera corporation 25 max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc input voltage on i/o pins is ?.5 v and on 4 dedicated input pins is ?.3 v. during transitions, the inputs may undershoot to ?.0 v or overshoot to 7.0 v for input currents less than 100 ma and periods shorter than 20 ns. (3) numbers in parentheses are for industrial-temperature-range devices. (4) v cc must rise monotonically. (5) 3.3-v i/o operation is not available for 44-pin packages. (6) the v ccisp parameter applies only to max 7000s devices. (7) during in-system programming, the minimum dc input voltage is ?.3 v. (8) these values are specified in table 11 on page 23 . (9) the parameter is measured with 50 % of the outputs each sourcing the specified current. the i oh parameter refers to high-level ttl or cmos output current. (10) the parameter is measured with 50 % of the outputs each sinking the specified current . the i ol parameter refers to low-level ttl or cmos output current. (11) when the jtag interface is enabled in max 7000s devices, the input leakage current on the jtag pins is typically ?0 ?. (12) capacitance is measured at 25 c and is sample-tested only. the oe1 pin has a maximum capacitance of 20 pf. figure 11 shows the typical output drive characteristics of max 7000 devices. figure 11. output drive characteristics of 5.0-v max 7000 devices t iming model max 7000 device timing can be analyzed with the quartus or max+plus ii software, with a variety of popular industry-standard eda simulators and timing analyzers, or with the timing model shown in figure 12 . max 7000 devices have fixed internal delays that enable the designer to determine the worst-case timing of any design. the quartus and max+plus ii software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for a device-wide performance evaluation. v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 3 0 6 0 9 0 1 5 0 1 2 0 v c c i o = 3 . 3 v i o l i o h r o o m t e m p e r a t u r e 3 . 3 v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 3 0 6 0 9 0 1 5 0 1 2 0 v c c i o = 5 . 0 v i o l i o h r o o m t e m p e r a t u r e i o t y p i c a l o u t p u t c u r r e n t ( m a ) i o t y p i c a l o u t p u t c u r r e n t ( m a ) 26 altera corporation max 7000 p r ogrammable logic d e vice f ami l y data sheet figure 12. max 7000 timing model notes: (1) only available in max 7000e and max 7000s devices. (2) not available in 44-pin devices. the timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. external timing parameters, which represent pin-to-pin timing delays, can be calculated as the sum of internal parameters. figure 13 shows the internal timing relationship of internal and external delay parameters. f see application note 94 (understanding max 7000 timing ) for more information. l o g i c a r r a y d e l a y t l a d o u t p u t d e l a y t o d 3 t o d 2 t o d 1 t x z z t x 1 t z x 2 t z x 3 i n p u t d e l a y t i n r e g i s t e r d e l a y t s u t h t p r e t c l r t r d t c o m b t f s u t f h p i a d e l a y t pia s h a r e d e x p a n d e r d e l a y t s e x p r e g i s t e r c o n t r o l d e l a y t l a c t i c t e n i / o d e l a y t i o g l o b a l c o n t r o l d e l a y t g l o b i n t e r n a l o u t p u t e n a b l e d e l a y t ioe p a r a l l e l e x p a n d e r d e l a y t p e x p f a s t i n p u t d e l a y t f i n ( 1 ) ( 2 ) ( 1 ) ( 1 ) ( 2 ) altera corporation 27 max 7000 pr ogrammab le logic de vice f amil y data sheet figure 13. switching w aveforms c o m b i n a t o r i a l m o d e i n p u t p i n i / o p i n p i a d e l a y s h a r e d e x p a n d e r d e l a y l o g i c a r r a y i n p u t p a r a l l e l e x p a n d e r d e l a y l o g i c a r r a y o u t p u t o u t p u t p i n t i n t l a c , t l a d t p i a t o d t p e x p t i o t s e x p t c o m b g l o b a l c l o c k m o d e g l o b a l c l o c k p i n g l o b a l c l o c k a t r e g i s t e r d a t a o r e n a b l e ( l o g i c a r r a y o u t p u t ) t f t c h t c l t r t i n t g l o b t s u t h a r r a y c l o c k m o d e i n p u t o r i / o p i n c l o c k i n t o p i a c l o c k i n t o l o g i c a r r a y c l o c k a t r e g i s t e r d a t a f r o m l o g i c a r r a y r e g i s t e r t o p i a t o l o g i c a r r a y r e g i s t e r o u t p u t t o p i n t f t r t a c h t a c l t s u t i n t i o t r d t p i a t c l r , t p r e t h t p i a t i c t p i a t o d t o d t r & t f < 3 ns. inputs are driven at 3 v for a logic high and 0 v for a logic low . all timing characteristics are measured at 1.5 v . 28 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet tables 16 through 23 show the max 7000 and max 7000e ac operating conditions. table 16. max 7000 & max 7000e external timing par ameters note (1) symbol parameter conditions speed grade unit -6 -7 min max min max t pd1 input to non-registered output c1 = 35 pf 6 .0 7.5 ns t pd2 i/o input to non-registered output c1 = 35 pf 6 .0 7.5 ns t su global clock setup time 5 .0 6 .0 ns t h global clock hold time 0 .0 0 .0 ns t fsu global clock setup time of fast input (2) 2.5 3 .0 ns t fh global clock hold time of fast input (2) 0.5 0.5 ns t co1 global clock to output delay c1 = 35 pf 4 .0 4.5 ns t ch global clock high time 2.5 3 .0 ns t cl global clock low time 2.5 3 .0 ns t asu array clock setup time 2.5 3 .0 ns t ah array clock hold time 2 .0 2 .0 ns t aco1 array clock to output delay c1 = 35 pf 6.5 7.5 ns t ach array clock high time 3 .0 3 .0 ns t acl array clock low time 3 .0 3 .0 ns t cppw minimum pulse width for clear and preset (3) 3.0 3.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 ns t cnt minimum global clock period 6.6 8 .0 ns f cnt maximum internal global clock frequency (5) 151.5 125 .0 mhz t acnt minimum array clock period 6.6 8 .0 ns f acnt maximum internal array clock frequency (5) 151.5 125 .0 mhz f max maximum clock frequency (6) 200 166.7 mhz altera corporation 29 max 7000 pr ogrammab le logic de vice f amil y data sheet table 17. max 7000 & max 7000e interna l timing parameters symbol parameter conditions speed grade unit -6 -7 min max min max t in input pad and buffer delay 0 .4 0 .5 ns t io i/o input pad and buffer delay 0 .4 0 .5 ns t fin fast input delay (2) 0.8 1.0 ns t sexp shared expander delay 3 .5 4.0 ns t pexp parallel expander delay 0 .8 0 .8 ns t lad logic array delay 2.0 3.0 ns t lac logic control array delay 2.0 3.0 ns t ioe internal output enable delay (2) 2.0 ns t od1 output buffer and pad delay slow slew rate = off, v ccio = 5.0 v c1 = 35 pf 2.0 2.0 ns t od2 output buffer and pad delay slow slew rate = off, v ccio = 3.3 v c1 = 35 pf (7) 2 .5 2 .5 ns t od3 output buffer and pad delay slow slew rate = on, v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 7.0 7.0 ns t zx1 output buffer enable delay slow slew rate = off, v ccio = 5.0 v c1 = 35 pf 4.0 4.0 ns t zx2 output buffer enable delay slow slew rate = off, v ccio = 3.3 v c1 = 35 pf (7) 4 .5 4 .5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 9.0 9.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 ns t su register setup time 3 .0 3 .0 ns t h register hold time 1.5 2 .0 ns t fsu register setup time of fast input (2) 2.5 3 .0 ns t fh register hold time of fast input (2) 0.5 0.5 ns t rd register delay 0 .8 1.0 ns t comb combinatorial delay 0 .8 1.0 ns t ic array clock delay 2 .5 3.0 ns t en register enable time 2.0 3.0 ns t glob global control delay 0 .8 1.0 ns t pre register preset time 2.0 2.0 ns t clr register clear time 2.0 2.0 ns t pia pia delay 0 .8 1.0 ns t lpa low-power adder (8) 10 .0 10 .0 ns 30 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 18. max 7000 & max 7000e external timing parameters symbol parameter conditions speed grade unit max 7000 e (- 10p ) max 7000 (-10 ) m ax 7000e (-10) min max min max t pd1 input to non-registered output c1 = 35 pf 10 .0 10 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 10 .0 10 .0 ns t su global clock setup time 7 .0 8 .0 ns t h global clock hold time 0 .0 0 .0 ns t fsu global clock setup time of fast input (2) 3 .0 3 .0 ns t fh global clock hold time of fast input (2) 0.5 0.5 ns t co1 global clock to output delay c1 = 35 pf 5 .0 5 ns t ch global clock high time 4 .0 4 .0 ns t cl global clock low time 4 .0 4 .0 ns t asu array clock setup time 2 .0 3 .0 ns t ah array clock hold time 3 .0 3 .0 ns t aco1 array clock to output delay c1 = 35 pf 10 .0 10 .0 ns t ach array clock high time 4 .0 4 .0 ns t acl array clock low time 4 .0 4 .0 ns t cppw minimum pulse width for clear and preset (3) 4.0 4.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 ns t cnt minimum global clock period 10 .0 10 .0 ns f cnt maximum internal global clock frequency (5) 100 .0 100 .0 mhz t acnt minimum array clock period 10 .0 10 .0 ns f acnt maximum internal array clock frequency (5) 100 .0 100 .0 mhz f max maximum clock frequency (6) 125 .0 125 .0 mhz altera corporation 31 max 7000 pr ogrammab le logic de vice f amil y data sheet table 19. max 7000 & max 7000e internal timing parameters symbol parameter conditions speed grade unit max 7000 e (- 10p ) max 7000 (-10 ) m ax 7000e (-10) min max min max t in input pad and buffer delay 0.5 1 .0 ns t io i/o input pad and buffer delay 0.5 1 .0 ns t fin fast input delay (2) 1 .0 1 .0 ns t sexp shared expander delay 5 .0 5 .0 ns t pexp parallel expander delay 0.8 0.8 ns t lad logic array delay 5 .0 5 .0 ns t lac logic control array delay 5 .0 5 .0 ns t ioe internal output enable delay (2) 2 .0 2 .0 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 1.5 2 .0 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 2 .0 2.5 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 5.5 6 .0 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 5 .0 5 .0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 5.5 5.5 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 9 .0 9 .0 ns t xz output buffer disable delay c1 = 5 pf 5 .0 5 .0 ns t su register setup time 2 .0 3 .0 ns t h register hold time 3 .0 3 .0 ns t fsu register setup time of fast input (2) 3 .0 3 .0 ns t fh register hold time of fast input (2) 0.5 0.5 ns t rd register delay 2 .0 1 .0 ns t comb combinatorial delay 2 .0 1 .0 ns t ic array clock delay 5 .0 5 .0 ns t en register enable time 5 .0 5 .0 ns t glob global control delay 1 .0 1 .0 ns t pre register preset time 3 .0 3 .0 ns t clr register clear time 3 .0 3 .0 ns t pia pia delay 1 .0 1 .0 ns t lpa low-power adder (8) 11 .0 11 .0 ns 32 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 20. max 7000 & max 7000e external timing parameters symbol parameter conditions speed grade unit max 7000e (-12p) max 7000 (-12) max 7000e (-12) min max min max t pd1 input to non-registered output c1 = 35 pf 12 .0 12 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 12 .0 12 .0 ns t su global clock setup time 7 .0 10 .0 ns t h global clock hold time 0 .0 0 .0 ns t fsu global clock setup time of fast input (2) 3 .0 3 .0 ns t fh global clock hold time of fast input (2) 0 .0 0 .0 ns t co1 global clock to output delay c1 = 35 pf 6 .0 6 .0 ns t ch global clock high time 4 .0 4 .0 ns t cl global clock low time 4 .0 4 .0 ns t asu array clock setup time 3 .0 4 .0 ns t ah array clock hold time 4 .0 4 .0 ns t aco1 array clock to output delay c1 = 35 pf 12 .0 12 .0 ns t ach array clock high time 5 .0 5 .0 ns t acl array clock low time 5 .0 5 .0 ns t cppw minimum pulse width for clear and preset (3) 5.0 5.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 ns t cnt minimum global clock period 11 .0 11 .0 ns f cnt maximum internal global clock frequency (5) 90.9 90.9 mhz t acnt minimum array clock period 11 .0 11 .0 ns f acnt maximum internal array clock frequency (5) 90.9 90.9 mhz f max maximum clock frequency (6) 125 .0 125 .0 mhz altera corporation 33 max 7000 pr ogrammab le logic de vice f amil y data sheet table 21. max 7000 & max 7000e internal timing parameters symbol parameter conditions speed grade unit max 7000e (-12p) max 7000 (-12) max 7000e (-12) min max min max t in input pad and buffer delay 1 .0 2 .0 ns t io i/o input pad and buffer delay 1 .0 2 .0 ns t fin fast input delay (2) 1 .0 1 .0 ns t sexp shared expander delay 7 .0 7 .0 ns t pexp parallel expander delay 1 .0 1 .0 ns t lad logic array delay 7 .0 5 .0 ns t lac logic control array delay 5 .0 5 .0 ns t ioe internal output enable delay (2) 2 .0 2 .0 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 1 .0 3 .0 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 2 .0 4 .0 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 5 .0 7 .0 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 6 .0 6 .0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 7 .0 7 .0 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 pf (2) 10 .0 10 .0 ns t xz output buffer disable delay c1 = 5 pf 6 .0 6 .0 ns t su register setup time 1 .0 4.0 ns t h register hold time 6 .0 4.0 ns t fsu register setup time of fast input (2) 4 .0 2.0 ns t fh register hold time of fast input (2) 0 .0 2.0 ns t rd register delay 2 .0 1 .0 ns t comb combinatorial delay 2 .0 1 .0 ns t ic array clock delay 5 .0 5 .0 ns t en register enable time 7 .0 5 .0 ns t glob global control delay 2 .0 0 .0 ns t pre register preset time 4 .0 3 .0 ns t clr register clear time 4 .0 3 .0 ns t pia pia delay 1 .0 1 .0 ns t lpa low-power adder (8) 12 .0 12 .0 ns 34 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 22. max 7000 & max 7000e external timing parameters symbol parameter conditions speed grade unit -15 -15t -20 min max min max min max t pd1 input to non-registered output c1 = 35 pf 15 .0 15 .0 20 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 15 .0 15 .0 20 .0 ns t su global clock setup time 11 .0 11 .0 12 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 ns t fsu global clock setup time of fast input (2) 3 .0 5 .0 ns t fh global clock hold time of fast input (2) 0 .0 0 .0 ns t co1 global clock to output delay c1 = 35 pf 8 .0 8.0 12 .0 ns t ch global clock high time 5 .0 6 .0 6 .0 ns t cl global clock low time 5 .0 6 .0 6 .0 ns t asu array clock setup time 4 .0 4 .0 5 .0 ns t ah array clock hold time 4 .0 4 .0 5 .0 ns t aco1 array clock to output delay c1 = 35 pf 15 .0 15 .0 20 .0 ns t ach array clock high time 6 .0 6.5 8 .0 ns t acl array clock low time 6 .0 6.5 8 .0 ns t cppw minimum pulse width for clear and preset (3) 6.0 6.5 8.0 ns t odh output data hold time after clock c1 = 35 pf (4) 1 .0 1 .0 1 .0 ns t cnt minimum global clock period 13 .0 13 .0 16 .0 ns f cnt maximum internal global clock frequency (5) 76.9 76.9 62.5 mhz t acnt minimum array clock period 13 .0 13.0 16 .0 ns f acnt maximum internal array clock frequency (5) 76.9 76.9 62.5 mhz f max maximum clock frequency (6) 100 83.3 83.3 mhz altera corporation 35 max 7000 pr ogrammab le logic de vice f amil y data sheet table 23. max 7000 & max 7000e internal timing parameters symbol parameter conditions speed grade unit -15 -15t -20 min max min max min max t in input pad and buffer delay 2 .0 2 .0 3 .0 ns t io i/o input pad and buffer delay 2 .0 2 .0 3 .0 ns t fin fast input delay (2) 2 .0 4 .0 ns t sexp shared expander delay 8 .0 10 .0 9 .0 ns t pexp parallel expander delay 1 .0 1 .0 2 .0 ns t lad logic array delay 6 .0 6 .0 8 .0 ns t lac logic control array delay 6 .0 6 .0 8 .0 ns t ioe internal output enable delay (2) 3 .0 4 .0 ns t od1 output buffer and pad delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 4 .0 4 .0 5 .0 ns t od2 output buffer and pad delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 5 .0 6 .0 ns t od3 output buffer and pad delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 p f (2) 8 .0 9 .0 ns t zx1 output buffer enable delay slow slew rate = off v ccio = 5.0 v c1 = 35 pf 6 .0 6 .0 10 .0 ns t zx2 output buffer enable delay slow slew rate = off v ccio = 3.3 v c1 = 35 pf (7) 7 .0 11 .0 ns t zx3 output buffer enable delay slow slew rate = on v ccio = 5.0 v or 3.3 v c1 = 35 p f (2) 10 .0 14 .0 ns t xz output buffer disable delay c1 = 5 pf 6 .0 6 .0 10 .0 ns t su register setup time 4 .0 4 .0 4 .0 ns t h register hold time 4 .0 4 .0 5 .0 ns t fsu register setup time of fast input (2) 2 .0 4 .0 ns t fh register hold time of fast input (2) 2 .0 3 .0 ns t rd register delay 1 .0 1 .0 1 .0 ns t comb combinatorial delay 1 .0 1 .0 1 .0 ns t ic array clock delay 6 .0 6 .0 8 .0 ns t en register enable time 6 .0 6 .0 8 .0 ns t glob global control delay 1 .0 1 .0 3 .0 ns t pre register preset time 4 .0 4 .0 4 .0 ns t clr register clear time 4 .0 4 .0 4 .0 ns t pia pia delay 2 .0 2 .0 3 .0 ns t lpa low-power adder (8) 13.0 15.0 15.0 ns 36 altera corporation max 7000 programmable logic device family data sheet notes to tables: (1) these values are specified in table 11 on page 23 . (2) this parameter applies to max 7000e devices only. (3) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (4) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (5) measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (6) the f max values represent the highest frequency for pipelined data. (7) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (8) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 24 and 25 show the epm7032s ac operating conditions. table 24. epm7032s external timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf 5.0 6.0 7.5 10.0 ns t pd2 i/o input to non-registered output c1 = 35 pf 5.0 6.0 7.5 10.0 ns t su global clock setup time 2.9 4.0 5.0 7.0 ns t h global clock hold time 0.0 0.0 0.0 0.0 ns t fsu global clock setup time of fast input 2.5 2.5 2.5 3.0 ns t fh global clock hold time of fast input 0.0 0.0 0.0 0.5 ns t co1 global clock to output delay c1 = 35 pf 3.2 3.5 4.3 5.0 ns t ch global clock high time 2.0 2.5 3.0 4.0 ns t cl global clock low time 2.0 2.5 3.0 4.0 ns t asu array clock setup time 0.7 0.9 1.1 2.0 ns t ah array clock hold time 1.8 2.1 2.7 3.0 ns t aco1 array clock to output delay c1 = 35 pf 5.4 6.6 8.2 10.0 ns t ach array clock high time 2.5 2.5 3.0 4.0 ns t acl array clock low time 2.5 2.5 3.0 4.0 ns t cppw minimum pulse width for clear and preset (1) 2.5 2.5 3.0 4.0 ns t odh output data hold time after clock c1 = 35 pf (2) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 5.7 7.0 8.6 10.0 ns f cnt maximum internal global clock frequency (3) 175.4 142.9 116.3 100.0 mhz t acnt minimum array clock period 5.7 7.0 8.6 10.0 ns altera corporation 37 max 7000 pr ogrammab le logic de vice f amil y data sheet f acnt maximum internal array clock frequency (3) 17 5.4 142.9 116.3 100.0 mhz f max maximum clock frequency (4) 250.0 200.0 166.7 125.0 mhz table 25. epm7032s internal timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max t in input pad and buffer delay 0. 2 0.2 0.3 0.5 ns t io i/o input pad and buffer delay 0. 2 0.2 0.3 0.5 ns t fin fast input delay 2 .2 2.1 2.5 1 .0 ns t sexp shared expander delay 3.1 3.8 4.6 5 .0 ns t pexp parallel expander delay 0. 9 1.1 1.4 0.8 ns t lad logic array delay 2.6 3.3 4 .0 5 .0 ns t lac logic control array delay 2.5 3.3 4 .0 5 .0 ns t ioe internal output enable delay 0. 7 0.8 1 .0 2 .0 ns t od1 output buffer and pad dela y c1 = 35 pf 0. 2 0.3 0.4 1.5 ns t od2 output buffer and pad dela y c1 = 35 pf (5) 0. 7 0.8 0.9 2 .0 ns t od3 output buffer and pad dela y c1 = 35 pf 5. 2 5.3 5.4 5.5 ns t zx1 output buffer enable dela y c1 = 35 pf 4 .0 4 .0 4 .0 5 .0 ns t zx2 output buffer enable dela y c1 = 35 pf (5) 4.5 4.5 4.5 5.5 ns t zx3 output buffer enable dela y c1 = 35 pf 9 .0 9 .0 9 .0 9 .0 ns t xz output buffer disable delay c1 = 5 pf 4 .0 4 .0 4 .0 5 .0 ns t su register setup time 0.8 1 .0 1.3 2 .0 ns t h register hold time 1.7 2 .0 2.5 3 .0 ns t fsu register setup time of fast input 1.9 1.8 1.7 3 .0 ns t fh register hold time of fast input 0.6 0.7 0.8 0.5 ns t rd register delay 1. 2 1.6 1.9 2 .0 ns t comb combinatorial delay 0.9 1.1 1.4 2 .0 ns t ic array clock delay 2. 7 3.4 4.2 5 .0 ns t en register enable time 2. 6 3.3 4 .0 5 .0 ns t glob global control delay 1. 6 1.4 1.7 1 .0 ns t pre register preset time 2.0 2.4 3 .0 3 .0 ns table 24. epm7032s external timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max 38 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (2) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (3) measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (4) the f max values represent the highest frequency for pipelined data. (5) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (6) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value . (7) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 26 and 27 show the epm7064s ac operating conditions. t clr register clear time 2.0 2.4 3 .0 3 .0 ns t pia pia delay (6) 1.1 1.1 1.4 1 .0 ns t lpa low-power adder (7) 12 .0 10 .0 10 .0 11 .0 ns table 25. epm7032s internal timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max table 26. epm7064s external timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf 5.0 6 .0 7.5 10 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 5.0 6 .0 7.5 10 .0 ns t su global clock setup time 2. 9 3. 6 6 .0 7 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 0 .0 ns t fsu global clock setup time of fast input 2.5 2.5 3 .0 3 .0 ns t fh global clock hold time of fast input 0 .0 0 .0 0.5 0.5 ns t co1 global clock to output delay c1 = 35 pf 3.2 4.0 4.5 5 .0 ns t ch global clock high time 2 .0 2.5 3 .0 4 .0 ns t cl global clock low time 2 .0 2.5 3 .0 4 .0 ns t asu array clock setup time 0 .7 0. 9 3 .0 2 .0 ns t ah array clock hold time 1 .8 2.1 2 .0 3 .0 ns altera corporation 39 max 7000 pr ogrammab le logic de vice f amil y data sheet t aco1 array clock to output delay c1 = 35 pf 5.4 6. 7 7.5 10 .0 ns t ach array clock high time 2.5 2.5 3 .0 4 .0 ns t acl array clock low time 2.5 2.5 3 .0 4 .0 ns t cppw minimum pulse width for clear and preset (1) 2.5 2.5 3.0 4.0 ns t odh output data hold time after clock c1 = 35 pf (2) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 5. 7 7.1 8 .0 10 .0 n s f cnt maximum internal global clock frequency (3) 17 5.4 1 40.8 125.0 100.0 mhz t acnt minimum array clock period 5. 7 7.1 8.0 10 .0 ns f acnt maximum internal array clock frequency (3) 17 5.4 14 0.8 125.0 100.0 mhz f max maximum clock frequency (4) 250.0 200.0 166.7 125.0 mhz table 27. epm7064s internal timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max t in input pad and buffer delay 0. 2 0.2 0.5 0.5 ns t io i/o input pad and buffer delay 0. 2 0.2 0.5 0.5 ns t fin fast input delay 2 .2 2. 6 1 .0 1 .0 ns t sexp shared expander delay 3.1 3.8 4 .0 5 .0 ns t pexp parallel expander delay 0. 9 1.1 0.8 0.8 ns t lad logic array delay 2.6 3.2 3 .0 5 .0 ns t lac logic control array delay 2.5 3.2 3 .0 5 .0 ns t ioe internal output enable delay 0. 7 0.8 2 .0 2 .0 ns t od1 output buffer and pad dela y c1 = 35 pf 0. 2 0.3 2 .0 1.5 ns t od2 output buffer and pad dela y c1 = 35 pf (5) 0. 7 0.8 2.5 2 .0 ns t od3 output buffer and pad dela y c1 = 35 p f 5. 2 5.3 7 .0 5.5 ns t zx1 output buffer enable dela y c1 = 35 pf 4 .0 4 .0 4 .0 5 .0 ns t zx2 output buffer enable dela y c1 = 35 pf (5) 4.5 4.5 4.5 5.5 ns t zx3 output buffer enable dela y c1 = 35 p f 9 .0 9 .0 9 .0 9 .0 ns t xz output buffer disable delay c1 = 5 p f 4 .0 4 .0 4 .0 5 .0 ns t su register setup time 0. 8 1.0 3 .0 2 .0 ns table 26. epm7064s external timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max 40 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (2) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (3) measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (4) the f max values represent the highest frequency for pipelined data. (5) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (6) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value . (7) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 28 and 29 show the epm7128s ac operating conditions. t h register hold time 1. 7 2.0 2 .0 3 .0 ns t fsu register setup time of fast input 1.9 1.8 3 .0 3 .0 ns t fh register hold time of fast input 0.6 0. 7 0.5 0.5 ns t rd register delay 1. 2 1. 6 1 .0 2 .0 ns t comb combinatorial delay 0.9 1 .0 1 .0 2 .0 ns t ic array clock delay 2. 7 3.3 3 .0 5 .0 ns t en register enable time 2. 6 3.2 3 .0 5 .0 ns t glob global control delay 1. 6 1. 9 1 .0 1 .0 ns t pre register preset time 2.0 2. 4 2 .0 3 .0 ns t clr register clear time 2.0 2. 4 2 .0 3 .0 ns t pia pia delay (6) 1.1 1. 3 1 .0 1 .0 ns t lpa low-power adder (7) 12 .0 11 .0 10 .0 11 .0 ns table 27. epm7064s internal timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -5 -6 -7 -10 min max min max min max min max altera corporation 41 max 7000 pr ogrammab le logic de vice f amil y data sheet table 28. epm7128s external timing parameters symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf 6 .0 7.5 10 .0 15 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 6 .0 7.5 10 .0 15 .0 ns t su global clock setup time 3.4 6 .0 7 .0 11 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 0 .0 ns t fsu global clock setup time of fast input 2.5 3 .0 3 .0 3 .0 ns t fh global clock hold time of fast input 0 .0 0.5 0.5 0 .0 ns t co1 global clock to output delay c1 = 35 pf 4 .0 4.5 5 .0 8 .0 ns t ch global clock high time 3 .0 3 .0 4 .0 5 .0 ns t cl global clock low time 3 .0 3 .0 4 .0 5 .0 ns t asu array clock setup time 0.9 3 .0 2 .0 4 .0 ns t ah array clock hold time 1.8 2 .0 5 .0 4 .0 ns t aco1 array clock to output delay c1 = 35 pf 6.5 7.5 10 .0 15 .0 ns t ach array clock high time 3 .0 3 .0 4 .0 6 .0 ns t acl array clock low time 3 .0 3 .0 4 .0 6 .0 ns t cppw minimum pulse width for clear and preset (1) 3.0 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 pf (2) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 6.8 8 .0 10 .0 13 .0 ns f cnt maximum internal global clock frequency (3) 147.1 125.0 100.0 76.9 mhz t acnt minimum array clock period 6.8 8 .0 10 .0 13 .0 ns f acnt maximum internal array clock frequency (3) 147.1 125.0 100.0 76.9 mhz f max maximum clock frequency (4) 166.7 166.7 125.0 100.0 mhz 42 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 29. epm7128s internal timing parameters symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max t in input pad and buffer delay 0.2 0.5 0.5 2 .0 ns t io i/o input pad and buffer delay 0.2 0.5 0.5 2 .0 ns t fin fast input delay 2.6 1 .0 1 .0 2 .0 ns t sexp shared expander delay 3.7 4 .0 5 .0 8 .0 ns t pexp parallel expander delay 1.1 0.8 0.8 1 .0 ns t lad logic array delay 3 .0 3 .0 5 .0 6 .0 ns t lac logic control array delay 3 .0 3 .0 5 .0 6 .0 ns t ioe internal output enable delay 0.7 2 .0 2 .0 3 .0 ns t od1 output buffer and pad dela y c1 = 35 pf 0.4 2 .0 1.5 4 .0 ns t od2 output buffer and pad dela y c1 = 35 pf (5) 0.9 2.5 2 .0 5 .0 ns t od3 output buffer and pad dela y c1 = 35 p f 5.4 7 .0 5.5 8 .0 ns t zx1 output buffer enable dela y c1 = 35 pf 4 .0 4 .0 5 .0 6 .0 ns t zx2 output buffer enable dela y c1 = 35 pf (5) 4.5 4.5 5.5 7 .0 ns t zx3 output buffer enable dela y c1 = 35 p f 9 .0 9 .0 9 .0 10 .0 ns t xz output buffer disable delay c1 = 5 p f 4 .0 4 .0 5 .0 6 .0 ns t su register setup time 1.0 3 .0 2 .0 4 .0 ns t h register hold time 1.7 2 .0 5 .0 4 .0 ns t fsu register setup time of fast input 1.9 3 .0 3 .0 2 .0 ns t fh register hold time of fast input 0.6 0.5 0.5 1.0 ns t rd register delay 1.4 1 .0 2 .0 1 .0 ns t comb combinatorial delay 1 .0 1 .0 2 .0 1 .0 ns t ic array clock delay 3.1 3 .0 5 .0 6 .0 ns t en register enable time 3 .0 3 .0 5 .0 6 .0 ns t glob global control delay 2 .0 1 .0 1 .0 1 .0 ns t pre register preset time 2.4 2 .0 3 .0 4 .0 ns t clr register clear time 2.4 2 .0 3 .0 4 .0 ns t pia pia delay (6) 1.4 1 .0 1 .0 2 .0 ns t lpa low-power adder (7) 11 .0 10 .0 11 .0 13 .0 ns altera corporation 43 max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (2) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (3) measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (4) the f max values represent the highest frequency for pipelined data. (5) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (6) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value . (7) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 30 and 31 show the epm7160s ac operating conditions. table 30. epm7160s external timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max t pd1 input to non-registered output c1 = 35 pf 6 .0 7.5 10 .0 15 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 6 .0 7.5 10 .0 15 .0 ns t su global clock setup time 3.4 4.2 7 .0 11 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 0 .0 ns t fsu global clock setup time of fast input 2.5 3 .0 3 .0 3 .0 ns t fh global clock hold time of fast input 0 .0 0 .0 0.5 0 .0 ns t co1 global clock to output delay c1 = 35 pf 3.9 4.8 5 8 ns t ch global clock high time 3 .0 3 .0 4 .0 5 .0 ns t cl global clock low time 3 .0 3 .0 4 .0 5 .0 ns t asu array clock setup time 0.9 1.1 2 .0 4 .0 ns t ah array clock hold time 1.7 2.1 3 .0 4 .0 ns t aco1 array clock to output delay c1 = 35 pf 6.4 7.9 10 .0 15 .0 ns t ach array clock high time 3 .0 3 .0 4 .0 6 .0 ns t acl array clock low time 3 .0 3 .0 4 .0 6 .0 ns t cppw minimum pulse width for clear and preset (1) 2.5 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 pf (2) 1.0 1.0 1.0 1.0 ns t cnt minimum global clock period 6.7 8.2 10 .0 13 .0 ns f cnt maximum internal global clock frequency (3) 149.3 122.0 100.0 76.9 mhz t acnt minimum array clock period 6.7 8.2 10 .0 13 .0 ns 44 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet f acnt maximum internal array clock frequency (3) 149.3 122.0 100.0 76.9 mhz f max maximum clock frequency (4) 166.7 166.7 125.0 100.0 mhz table 31. epm7160s internal timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max t in input pad and buffer delay 0.2 0.3 0.5 2 .0 ns t io i/o input pad and buffer delay 0.2 0.3 0.5 2 .0 ns t fin fast input delay 2.6 3.2 1 .0 2 .0 ns t sexp shared expander delay 3.6 4.3 5 .0 8 .0 ns t pexp parallel expander delay 1 .0 1.3 0.8 1 .0 ns t lad logic array delay 2.8 3.4 5 .0 6 .0 ns t lac logic control array delay 2.8 3.4 5 .0 6 .0 ns t ioe internal output enable delay 0.7 0.9 2 .0 3 .0 ns t od1 output buffer and pad dela y c1 = 35 pf 0.4 0.5 1.5 4 .0 ns t od2 output buffer and pad dela y c1 = 35 pf (5) 0.9 1 .0 2 .0 5 .0 ns t od3 output buffer and pad dela y c1 = 35 p f 5.4 5.5 5.5 8 .0 ns t zx1 output buffer enable dela y c1 = 35 pf 4 .0 4 .0 5 .0 6 .0 ns t zx2 output buffer enable dela y c1 = 35 pf (5) 4.5 4.5 5.5 7 .0 ns t zx3 output buffer enable dela y c1 = 35 p f 9 .0 9 .0 9 .0 10 .0 ns t xz output buffer disable delay c1 = 5 p f 4 .0 4 .0 5 .0 6 .0 ns t su register setup time 1.0 1.2 2 .0 4 .0 ns t h register hold time 1.6 2 .0 3 .0 4 .0 ns t fsu register setup time of fast input 1.9 2.2 3 .0 2 .0 ns t fh register hold time of fast input 0.6 0.8 0.5 1 .0 ns t rd register delay 1.3 1.6 2 .0 1 .0 ns t comb combinatorial delay 1 .0 1.3 2 .0 1 .0 ns t ic array clock delay 2.9 3.5 5 .0 6 .0 ns t en register enable time 2.8 3.4 5 .0 6 .0 ns t glob global control delay 2 .0 2.4 1 .0 1 .0 ns t pre register preset time 2.4 3 .0 3 .0 4 .0 ns table 30. epm7160s external timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max altera corporation 45 max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (2) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (3) measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (4) the f max values represent the highest frequency for pipelined data. (5) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (6) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value . (7) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. tables 32 and 33 show the epm7192s ac operating conditions. t clr register clear time 2.4 3 .0 3 .0 4 .0 ns t pia pia delay (6) 1.6 2 .0 1 .0 2 .0 ns t lpa low-power adder (7) 11 .0 10 .0 11 .0 13 .0 ns table 31. epm7160s internal timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -6 -7 -10 -15 min max min max min max min max table 32. epm7192s external timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max t pd1 input to non-registered output c1 = 35 pf 7.5 10 .0 15 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 7.5 10 .0 15 .0 ns t su global clock setup time 4.1 7 .0 11 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 ns t fsu global clock setup time of fast input 3 .0 3 .0 3 .0 ns t fh global clock hold time of fast input 0 .0 0.5 0 .0 ns t co1 global clock to output delay c1 = 35 pf 4.7 5 .0 8 .0 ns t ch global clock high time 3 .0 4 .0 5 .0 ns t cl global clock low time 3 .0 4 .0 5 .0 ns t asu array clock setup time 1 .0 2 .0 4 .0 ns t ah array clock hold time 1.8 3 .0 4 .0 ns t aco1 array clock to output delay c1 = 35 pf 7.8 10 .0 15 .0 ns 46 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet t ach array clock high time 3 .0 4 .0 6 .0 ns t acl array clock low time 3 .0 4 .0 6 .0 ns t cppw minimum pulse width for clear and preset (1) 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 p f (2) 1 .0 1 .0 1 .0 ns t cnt minimum global clock period 8 .0 10 .0 13 .0 ns f cnt maximum internal global clock frequency (3) 125.0 100.0 76.9 mhz t acnt minimum array clock period 8 .0 10 .0 13 .0 ns f acnt maximum internal array clock frequency (3) 125.0 100.0 76.9 mhz f max maximum clock frequency (4) 166.7 125.0 100.0 mhz table 33. epm7192s internal timing parameters (part 1 of 2) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max t in input pad and buffer delay 0.3 0.5 2 .0 ns t io i/o input pad and buffer delay 0.3 0.5 2 .0 ns t fin fast input delay 3.2 1 .0 2 .0 ns t sexp shared expander delay 4.2 5 .0 8 .0 ns t pexp parallel expander delay 1.2 0.8 1 .0 ns t lad logic array delay 3.1 5 .0 6 .0 ns t lac logic control array delay 3.1 5 .0 6 .0 ns t ioe internal output enable delay 0.9 2 .0 3 .0 ns t od1 output buffer and pad dela y c1 = 35 pf 0.5 1.5 4 .0 ns t od2 output buffer and pad dela y c1 = 35 pf (5) 1 .0 2 .0 5 .0 ns t od3 output buffer and pad dela y c1 = 35 pf 5.5 5.5 7 .0 ns t zx1 output buffer enable dela y c1 = 35 pf 4 .0 5 .0 6 .0 ns t zx2 output buffer enable dela y c1 = 35 pf (5) 4.5 5.5 7 .0 ns t zx3 output buffer enable dela y c1 = 35 pf 9 .0 9 .0 10 .0 ns t xz output buffer disable delay c1 = 5 pf 4 .0 5 .0 6 .0 ns t su register setup time 1.1 2 .0 4 .0 ns t h register hold time 1.7 3 .0 4 .0 ns table 32. epm7192s external timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max altera corporation 47 max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (2) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (3) measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (4) the f max values represent the highest frequency for pipelined data. (5) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (6) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value . (7) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. t fsu register setup time of fast input 2.3 3 .0 2 .0 ns t fh register hold time of fast input 0.7 0.5 1 .0 ns t rd register delay 1.4 2 .0 1 .0 ns t comb combinatorial delay 1.2 2 .0 1 .0 ns t ic array clock delay 3.2 5 .0 6 .0 ns t en register enable time 3.1 5 .0 6 .0 ns t glob global control delay 2.5 1 .0 1 .0 ns t pre register preset time 2.7 3 .0 4 .0 ns t clr register clear time 2.7 3 .0 4 .0 ns t pia pia delay (6) 2.4 1 .0 2 .0 ns t lpa low-power adder (7) 10 .0 11 .0 13 .0 ns table 33. epm7192s internal timing parameters (part 2 of 2) symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max 48 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet tables 34 and 35 show the epm7256s ac operating conditions. table 34. epm7256s external timing parameters symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max t pd1 input to non-registered output c1 = 35 pf 7.5 10 .0 15 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 7.5 10 .0 15 .0 ns t su global clock setup time 3.9 7 .0 11 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 ns t fsu global clock setup time of fast input 3 .0 3 .0 3 .0 ns t fh global clock hold time of fast input 0 .0 0.5 0 .0 ns t co1 global clock to output delay c1 = 35 pf 4.7 5 .0 8 .0 ns t ch global clock high time 3 .0 4 .0 5 .0 ns t cl global clock low time 3 .0 4 .0 5 .0 ns t asu array clock setup time 0.8 2 .0 4 .0 ns t ah array clock hold time 1.9 3 .0 4 .0 ns t aco1 array clock to output delay c1 = 35 pf 7.8 10 .0 15 .0 ns t ach array clock high time 3 .0 4 .0 6 .0 ns t acl array clock low time 3 .0 4 .0 6 .0 ns t cppw minimum pulse width for clear and preset (1) 3.0 4.0 6.0 ns t odh output data hold time after clock c1 = 35 pf (2) 1 .0 1 .0 1 .0 ns t cnt minimum global clock period 7.8 10 .0 13 .0 ns f cnt maximum internal global clock frequency (3) 128.2 100.0 76.9 mhz t acnt minimum array clock period 7.8 10 .0 13 .0 ns f acnt maximum internal array clock frequency (3) 128.2 100.0 76.9 mhz f max maximum clock frequency (4) 166.7 125.0 100.0 mhz altera corporation 49 max 7000 pr ogrammab le logic de vice f amil y data sheet table 35. epm7256s internal timing parameters symbol parameter conditions speed grade unit -7 -10 -15 min max min max min max t in input pad and buffer delay 0.3 0.5 2 .0 ns t io i/o input pad and buffer delay 0.3 0.5 2 .0 ns t fin fast input delay 3.4 1 .0 2 .0 ns t sexp shared expander delay 3.9 5 .0 8 .0 ns t pexp parallel expander delay 1.1 0.8 1 .0 ns t lad logic array delay 2.6 5 .0 6 .0 ns t lac logic control array delay 2.6 5 .0 6 .0 ns t ioe internal output enable delay 0.8 2 .0 3 .0 ns t od1 output buffer and pad dela y c1 = 35 pf 0.5 1.5 4 .0 ns t od2 output buffer and pad dela y c1 = 35 pf (5) 1 .0 2 .0 5 .0 ns t od3 output buffer and pad dela y c1 = 35 pf 5.5 5.5 8 .0 ns t zx1 output buffer enable dela y c1 = 35 pf 4 .0 5 .0 6 .0 ns t zx2 output buffer enable dela y c1 = 35 pf (5) 4.5 5.5 7 .0 ns t zx3 output buffer enable dela y c1 = 35 pf 9 .0 9 .0 10 .0 ns t xz output buffer disable delay c1 = 5 pf 4 .0 5 .0 6 .0 ns t su register setup time 1.1 2 .0 4 .0 ns t h register hold time 1.6 3 .0 4 .0 ns t fsu register setup time of fast input 2.4 3 .0 2 .0 ns t fh register hold time of fast input 0.6 0.5 1 .0 ns t rd register delay 1.1 2 .0 1 .0 ns t comb combinatorial delay 1.1 2 .0 1 .0 ns t ic array clock delay 2.9 5 .0 6 .0 ns t en register enable time 2.6 5 .0 6 .0 ns t glob global control delay 2.8 1 .0 1 .0 ns t pre register preset time 2.7 3 .0 4 .0 ns t clr register clear time 2.7 3 .0 4 .0 ns t pia pia delay (6) 3 .0 1 .0 2 .0 ns t lpa low-power adder (7) 10 .0 11 .0 13 .0 ns 50 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (2) this parameter is a guideline that is sample-tested only and is based on extensive device characterization. this parameter applies for both global and array clocking. (3) measured with a 16-bit loadable, enabled, up/down counter programmed into each lab. (4) the f max values represent the highest frequency for pipelined data. (5) operating conditions: v ccio = 3.3 v 10 % for commercial and industrial use. (6) for epm7064s-5, epm7064s-6, epm7128s-6, epm7160s-6, epm7160s-7, epm7192s-7, and epm7256s-7 devices, these values are specified for a pia fan-out of one lab (16 macrocells). for each additional lab fan-out in these devices, add an additional 0.1 ns to the pia timing value . (7) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in the low-power mode. power consu mption supply power (p) versus frequency ( f max in mhz) for max 7000 devices is calculated with the following equation: p = p int + p io = i cc int v cc + p io the p io value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in application note 74 (evaluating power for altera devices) . the i ccint value , which d epends on the switching frequency and the application logic , i s calculated with the following equation: i ccint = a mc ton + b (mc dev ?mc ton ) + c mc used f max tog lc the parameters in this equation are shown below: mc ton = number of macrocells with the turbo bit option turned on, as reported in the max+plus ii report file ( .rpt ) mc dev = number of macrocells in the device mc used = total number of macrocells in the design, as reported in the max+plus ii report file ( .rpt ) f max = highest clock frequency to the device tog lc = average ratio of logic cells toggling at each clock (typically 0.125) a, b, c = constants, shown in table 36 altera corporation 51 max 7000 pr ogrammab le logic de vice f amil y data sheet t his calculation provides an i cc estimate based on typical conditions using a pattern of a 16-bit, loadable, enabled, up/down counter in each lab with no output load. actual i cc values should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. table 36. max 7000 i cc equation constants device a b c epm7032 1.87 0.52 0.144 epm7064 1.63 0.74 0.144 epm7096 1.63 0.74 0.144 epm7128e 1.17 0.54 0.096 epm7160e 1.17 0.54 0.096 epm7192e 1.17 0.54 0.096 epm7256e 1.17 0.54 0.096 epm7032s 0.93 0.40 0.040 epm7064s 0.93 0.40 0.040 epm7128s 0.93 0.40 0.040 epm7160s 0.93 0.40 0.040 epm7192s 0.93 0.40 0.040 epm7256s 0.93 0.40 0.040 52 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet figure 14 shows typical supply current versus frequency for max 7000 devices. figure 14. i cc vs. frequency for max 7000 devices (part 1 of 2) f r e q u e n c y ( m h z ) e p m 7 0 6 4 e p m 7 0 3 2 0 5 0 f r e q u e n c y ( m h z ) 2 0 0 1 0 0 1 5 0 h i g h s p e e d 1 5 1 . 5 m h z 1 8 0 2 0 6 0 1 0 0 1 4 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 5 0 2 0 0 1 0 0 1 5 0 l o w p o w e r 6 0 . 2 m h z 1 5 1 . 5 m h z 2 0 0 3 0 0 1 0 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e e p m 7 0 9 6 0 5 0 f r e q u e n c y ( m h z ) 2 5 0 1 0 0 5 0 1 5 0 3 5 0 4 5 0 1 5 0 h i g h s p e e d v c c = 5 . 0 v r o o m t e m p e r a t u r e l o w p o w e r t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c 6 0 . 2 m h z 1 2 5 m h z 5 5 . 5 m h z h i g h s p e e d l o w p o w e r altera corporation 53 max 7000 pr ogrammab le logic de vice f amil y data sheet figure 14. i cc vs. frequency for max 7000 devices (part 2 of 2) v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) 5 0 0 3 0 0 7 5 4 0 0 2 0 0 1 0 0 2 5 5 0 1 0 0 1 2 5 9 0 . 9 m h z 4 3 . 5 m h z e p m 7 1 9 2 e v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) 7 5 0 4 5 0 7 5 6 0 0 3 0 0 1 5 0 2 5 5 0 1 0 0 9 0 . 9 m h z 4 3 . 4 m h z e p m 7 2 5 6 e v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) 5 0 0 3 0 0 4 0 0 l o w p o w e r 2 0 0 1 0 0 5 0 1 0 0 1 0 0 m h z 4 7 . 6 m h z e p m 7 1 6 0 e 1 5 0 2 0 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) 5 0 0 3 0 0 4 0 0 h i g h s p e e d 2 0 0 1 0 0 5 0 1 0 0 1 2 5 m h z 5 5 . 5 m h z e p m 7 1 2 8 e 1 5 0 2 0 0 h i g h s p e e d h i g h s p e e d h i g h s p e e d l o w p o w e r l o w p o w e r l o w p o w e r t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c 1 2 5 54 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet figure 15 shows typical supply current versus frequency for max 7000s devices. figure 15. i cc vs. frequency for max 7000s devices (part 1 of 2 ) v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 5 0 1 0 0 1 5 0 2 0 0 1 4 2 . 9 m h z 5 8 . 8 m h z e p m 7 0 3 2 s 1 0 2 0 3 0 4 0 5 0 6 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 5 0 1 0 0 1 5 0 2 0 0 1 7 5 . 4 m h z 5 6 . 5 m h z e p m 7 0 6 4 s 2 0 4 0 6 0 8 0 1 0 0 1 2 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 5 0 1 0 0 1 5 0 2 0 0 1 4 7 . 1 m h z 5 6 . 2 m h z e p m 7 1 2 8 s 8 0 1 2 0 2 0 0 2 8 0 1 6 0 4 0 2 4 0 v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 5 0 1 0 0 1 5 0 2 0 0 1 4 9 . 3 m h z 5 6 . 5 m h z e p m 7 1 6 0 s 6 0 1 2 0 1 8 0 2 4 0 3 0 0 t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c altera corporation 55 max 7000 pr ogrammab le logic de vice f amil y data sheet figure 15. i cc vs. frequency for max 7000s devices (part 2 of 2 ) device pin-outs tables 37 through 51 show the pin names and numbers for the pins in each max 7000 device package. e p m 7 1 9 2 s v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 2 5 1 0 0 1 2 5 1 2 5 . 0 m h z 5 5 . 6 m h z 6 0 1 2 0 1 8 0 2 4 0 3 0 0 5 0 7 5 e p m 7 2 5 6 s v c c = 5 . 0 v r o o m t e m p e r a t u r e 0 f r e q u e n c y ( m h z ) h i g h s p e e d l o w p o w e r 2 5 1 0 0 1 2 5 1 2 8 . 2 m h z 5 6 . 2 m h z 1 0 0 2 0 0 3 0 0 4 0 0 5 0 7 5 t y p i c a l i a c t i v e ( m a ) c c t y p i c a l i a c t i v e ( m a ) c c table 37. epm7032 & epm7032s dedic ated pin-outs pin name 44-pin plcc 44-pin pqfp/tqfp (1) input / gclk1 43 37 input/gclrn 1 39 input/oe 1 44 38 input/oe2/gclk2 (2) 2 40 tdi (3) 7 1 tms (3) 13 7 tck (3) 32 26 tdo (3) 38 32 pdn (4) 3 41 gnd 10, 22, 30, 42 4, 16, 24, 36 vcc 3, 15, 23, 35 9, 17, 29, 41 no connect (n.c.) total user i/o pins (5) 36 36 56 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) epm7032s and epm7032v devices are not available in the 44-pin pqfp package. (2) the gclk2 function is available in max 7000s and max 7000e devices only. (3) this jtag pin applies to m ax 7000s devices only and t his pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for isp, this pin is not available as a user i/o pin. (4) th e p dn pin is available in epm7032v devices only. (5) the user i/o pin count includes dedicated input pins and all i/o pins. table 38. epm7032 & epm7032s i/o pin-outs lab mc 44-pin plcc 44-pin pqfp/tqfp (1) lab mc 44-pi n plcc 44-pin pqfp/tqfp (1) a 1 4 42 b 17 41 35 2 5 43 18 40 34 3 6 44 19 39 33 4 7 (3) 1 (3) 20 38 (3) 32 (3) 5 8 2 21 37 31 6 9 3 22 36 30 7 11 5 23 34 28 8 12 6 24 33 27 9 13 (3) 7 (3) 25 32 (3) 26 (3) 10 14 8 26 31 25 11 16 10 27 29 23 12 17 11 28 28 22 13 18 12 29 27 21 14 19 13 30 26 20 15 20 14 31 25 19 16 21 15 32 24 18 altera corporation 57 max 7000 pr ogrammab le logic de vice f amil y data sheet table 39. epm7064 & epm7064s dedicated pin-outs dedicated pin 44-pin plcc 44-pin tqfp 68-pin plcc (1) 84-pin plcc 100-pin tqfp (2) 100-pin pqfp (1) input / gclk1 43 37 67 83 87 89 input / gclrn 1 39 1 1 89 91 input / oe1 44 38 68 84 88 90 input / oe2/gclk2 (3) 2 40 2 2 90 92 tdi (4) 7 1 12 14 4 6 tms (4) 13 7 19 23 15 17 tck (4) 32 26 50 62 62 64 tdo (4) 38 32 57 71 73 75 gnd 10, 22, 30, 42 4, 16, 24, 36 6, 16, 26, 34, 38, 48, 58, 66 7, 19, 32, 42, 47, 59, 72, 82 38, 86, 11, 26, 43, 59, 74, 95 13, 28, 40, 45, 61, 76, 88, 97 vccint (5.0 v only) 3, 15, 23, 35 9, 17, 29, 41 3, 35 3, 43 39, 91 41, 93 vccio (3.3 v or 5.0 v) 11, 21, 31, 43, 53, 63 13, 26, 38, 53, 66, 78 3, 18, 34, 51, 66, 82 5, 20, 36, 53, 68, 84 no connect (n.c.) 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 1, 2, 7, 9, 24, 26, 29, 30, 51, 52, 55, 57, 72, 74, 79, 80 total user i/o pins (5) 32 32 48 64 64 64 58 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 40. epm7064 & epm7064s i/o pin-outs (44-pin plcc, 44-pin tqfp & 68-pin plcc p ackages) lab mc 44-pin plcc 44-pin tqfp 68-pin plcc (1) lab mc 44-pi n plcc 44-pin tqfp 68-pin plcc (1) a 1 12 6 18 c 33 24 18 36 2 34 3 11 5 17 35 25 19 37 4 9 3 15 36 26 20 39 5 8 2 14 37 27 21 40 6 13 38 41 7 39 8 7 (4) 1 (4) 12 (4) 40 28 22 42 9 10 41 29 23 44 10 42 11 6 44 9 43 45 12 8 44 46 13 7 45 47 14 5 43 5 46 31 25 49 15 47 16 4 42 4 48 32 (4) 26 (4) 50 (4) b 17 21 15 33 d 49 33 27 51 18 50 19 20 14 32 51 34 28 52 20 19 13 30 52 36 30 54 21 18 12 29 53 37 31 55 22 28 54 56 23 55 24 17 11 27 56 38 (4) 32 (4) 57 (4) 25 16 10 25 57 39 33 59 26 58 27 24 59 60 28 23 60 61 29 22 61 62 30 14 8 20 62 40 34 64 31 63 32 13 (4) 7 (4) 19 (4) 64 41 35 65 altera corporation 59 max 7000 pr ogrammab le logic de vice f amil y data sheet table 41. epm7064 & epm7064s i/o pin-outs (84-pin plcc, 100-pin tqfp & 100-pin pqfp packages) lab mc 84-pin plcc 100-pin tqfp (2) 100-pin pqfp (1) lab mc 84-pin plcc 100-pin tqfp (2) 100-pin pqfp (1) a 1 22 14 16 c 33 44 40 42 2 21 13 15 34 45 41 43 3 20 12 14 35 46 42 44 4 18 10 12 36 48 44 46 5 17 9 11 37 49 45 47 6 16 8 10 38 50 46 48 7 15 6 8 39 51 47 49 8 14 (4) 4 (4) 6 (4) 40 52 48 50 9 12 100 4 41 54 52 54 10 11 99 3 42 55 54 56 11 10 98 100 43 56 56 58 12 9 97 99 44 57 57 59 13 8 96 98 45 58 58 60 14 6 94 96 46 60 60 62 15 5 93 95 47 61 61 63 16 4 92 94 48 62 (4) 62 (4) 64 (4) b 17 41 37 39 d 49 63 63 65 18 40 36 38 50 64 64 66 19 39 35 37 51 65 65 67 20 37 33 35 52 67 67 69 21 36 32 34 53 68 68 70 22 35 31 33 54 69 69 71 23 34 30 32 55 70 71 73 24 33 29 31 56 71 (4) 73 (4) 75 (4) 25 31 25 27 57 73 75 77 26 30 23 25 58 74 76 78 27 29 21 23 59 75 79 81 28 28 20 22 60 76 80 82 29 27 19 21 61 77 81 83 30 25 17 19 62 79 83 85 31 24 16 18 63 80 84 86 32 23 (4) 15 (4) 17 (4) 64 81 85 87 60 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) epm7064s devices are not available in the 100-pin pqfp package or 68-pin plcc packages. (2) epm7064 devices are not available in the 100-pin tqfp package. (3) the gclk2 function is available in max 7000s and max 7000e devices only. (4) this jtag pin applies to max 7000s devices only and this pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for isp, this pin is not available as a user i/o pin. (5) the user i/o pin count includes dedicated input pins and all i/o pins. note: (1) the user i/o pin count includes dedicated input pins and all i/o pins. table 42. epm7096 dedicated pin-outs dedicated pin 68-pin plcc 84-pin plcc 100-pin pqfp input / gclk1 67 83 89 input / gclrn 1 1 91 input / oe1 68 84 90 input / oe2 2 2 92 gnd 6, 16, 26, 34, 38, 48, 58, 66 7, 19, 32, 42, 47, 59, 72, 82 13, 28, 40, 45, 61, 76, 88, 97 vccint (5.0 v on ly) 3, 35 3, 43 41, 93 vccio (3.3 v or 5.0 v) 11, 21, 31, 43, 53, 63 13, 26, 38, 53, 66, 78 5, 20, 36, 53, 68, 84 no connect (n.c.) 6, 39, 46, 79 9, 24, 37, 44, 57, 72, 85, 96 total user i/o pins (1) 48 60 72 altera corporation 61 max 7000 pr ogrammab le logic de vice f amil y data sheet table 43. epm7096 i/o pin-outs (part 1 of 2) lab mc 68-pin plcc 84-pin plcc 100-pin pqfp lab mc 68-pin plcc 84-pin plcc 100-pin pqfp a 1 13 16 8 b 17 23 28 23 2 18 3 15 7 19 22 27 22 4 12 14 6 20 21 5 4 21 20 25 19 6 10 12 3 22 24 18 7 23 8 9 11 2 24 19 23 17 9 8 10 1 25 18 22 16 10 26 11 9 100 27 17 21 15 12 7 8 99 28 20 14 13 98 29 15 18 12 14 5 5 95 30 11 15 31 16 4 4 94 32 14 17 10 62 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet c 33 33 41 39 e 65 46 57 58 34 66 35 32 40 38 67 47 58 59 36 35 68 60 37 30 37 34 69 49 60 62 38 36 33 70 61 63 39 71 40 29 35 32 72 50 62 64 41 28 34 31 73 51 63 65 42 74 43 27 33 30 75 52 64 66 44 29 76 65 67 45 25 31 27 77 54 67 69 46 30 26 78 70 47 79 48 24 29 25 80 55 68 71 d 49 36 44 42 f 81 56 69 73 50 82 51 37 45 43 83 70 74 52 46 84 57 71 75 53 39 48 47 85 77 54 49 48 86 59 73 78 55 87 56 40 50 49 88 60 74 79 57 41 51 50 89 61 75 80 58 90 59 42 52 51 91 76 81 60 52 92 62 77 82 61 44 54 54 93 83 62 55 55 94 64 80 86 63 95 64 45 56 56 96 65 81 87 table 43. epm7096 i/o pin-outs (part 2 of 2) lab mc 68-pin plcc 84-pin plcc 100-pin pqfp lab mc 68-pin plcc 84-pin plcc 100-pin pqfp altera corporation 63 max 7000 pr ogrammab le logic de vice f amil y data sheet table 44. epm7128e & epm7128s dedicated pin-outs dedicated pin 84-pin plcc 100-pin pqfp 100-pin tqfp (1) , (2) 160-pin pqfp input / gclk1 83 89 87 139 input / gclrn 1 91 89 141 input / oe1 84 90 88 140 input / oe2 / gclk2 2 92 90 142 tdi (3) 14 6 4 9 tms (3) 23 17 15 22 tck (3) 62 64 62 99 tdo (3) 71 75 73 112 gndint 42, 82 40, 88 38, 86 60, 138 gndio 7, 19, 32,47, 59, 72 13, 28, 45, 61, 76, 97 11, 26, 43, 59, 74, 95 17, 42, 66, 95, 113, 148 vccint (5.0 v only) 3, 43 41, 93 39, 91 61, 143 vccio (3.3 v or 5.0 v) 13, 26, 38, 53, 66, 78 5, 20, 36, 53, 68, 84 3, 18, 34, 51, 66, 82 8, 26, 55, 79, 104, 133 no connect (n.c.) 1, 2, 3, 4, 5, 6, 7, 34, 35, 36, 37, 38, 39, 40, 44, 45, 46, 47, 74, 75, 76, 77, 81, 82, 83, 84, 85, 86, 87, 114, 115, 116, 117, 118, 119, 120, 124, 125, 126, 127, 154, 155, 156, 157 total user i/o pins (4) 64 80 80 96 64 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 45. epm7128e & epm7128s i/o pin-outs (part 1 of 2) lab mc 84-pin plcc 100-pin pqfp 100-pin tqf p (1) , (2) 160-pin pqfp lab mc 84-pin plcc 100-pin pqfp 100-pin tqf p (1) , (2) 160-pin pqfp a 1 4 2 160 c 33 27 25 41 2 34 3 12 3 1 159 35 31 26 24 33 4 158 36 32 5 11 2 100 153 37 30 25 23 31 6 10 1 99 152 38 29 24 22 30 7 39 8 9 100 98 151 40 28 23 21 29 9 99 97 150 41 22 20 28 10 42 11 8 98 96 149 43 27 21 19 27 12 147 44 25 13 6 96 94 146 45 25 19 17 24 14 5 95 93 145 46 24 18 16 23 15 47 16 4 94 92 144 48 23 (3) 17 (3) 15 (3) 22 (3) b 17 22 16 14 21 d 49 41 39 37 59 18 50 19 21 15 13 20 51 40 38 36 58 20 19 52 57 21 20 14 12 18 53 39 37 35 56 22 12 10 16 54 35 33 54 23 55 24 18 11 9 15 56 37 34 32 53 25 17 10 8 14 57 36 33 31 52 26 58 27 16 9 7 13 59 35 32 30 51 28 12 60 50 29 15 8 6 11 61 34 31 29 49 30 7 5 10 62 30 28 48 31 63 32 14 (3) 6 (3) 4 (3) 9 (3) 64 33 29 27 43 altera corporation 65 max 7000 pr ogrammab le logic de vice f amil y data sheet e 65 44 42 40 62 g 97 63 65 63 100 66 98 67 45 43 41 63 99 64 66 64 101 68 64 100 102 69 46 44 42 65 101 65 67 65 103 70 46 44 67 102 69 67 105 71 103 72 48 47 45 68 104 67 70 68 106 73 49 48 46 69 105 68 71 69 107 74 106 75 50 49 47 70 107 69 72 70 108 76 71 108 109 77 51 50 48 72 109 70 73 71 110 78 51 49 73 110 74 72 111 79 111 80 52 52 50 78 112 71 (3) 75 (3) 73 (3) 112 (3) f 81 54 52 80 h 113 77 75 121 82 114 83 54 55 53 88 115 73 78 76 122 84 89 116 123 85 55 56 54 90 117 74 79 77 128 86 56 57 55 91 118 75 80 78 129 87 119 88 57 58 56 92 120 76 81 79 130 89 59 57 93 121 82 80 131 90 122 91 58 60 58 94 123 77 83 81 132 92 96 124 134 93 60 62 60 97 125 79 85 83 135 94 61 63 61 98 126 80 86 84 136 95 127 96 62 (3) 64 (3) 62 (3) 99 (3) 128 81 87 85 137 table 45. epm7128e & epm7128s i/o pin-outs (part 2 of 2) lab mc 84-pin plcc 100-pin pqfp 100-pin tqf p (1) , (2) 160-pin pqfp lab mc 84-pin plcc 100-pin pqfp 100-pin tqf p (1) , (2) 160-pin pqfp 66 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) a complete thermal analysis should be performed before committing a design to this device package. (2) epm7128e devices are not available in the 100-pin tqfp package. (3) t his jtag pin applies to m ax 7000s devices only and t his pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for boundary-scan testing or for isp, this pin is not available as a user i/o pin. (4) the user i/o pin count includes dedicated input pins and all i/o pins. table 46. epm7160e & epm7160s dedicated pin-outs dedicated pin 84-pin plcc 100-pin tqfp (1) , (2) 100-pin pqfp (3) 160-pin pqfp input / gclk1 83 87 89 139 input / gclrn 1 89 91 141 input / oe1 84 88 90 140 input / oe2 / gclk2 2 90 92 142 tdi (4) 14 4 6 9 tms (4) 23 15 17 22 tck (4) 62 62 64 99 tdo (4) 71 73 75 112 gnd 7, 19, 32, 42, 47, 59, 72, 82 38, 86, 11, 26, 43, 59, 74, 95 13, 28, 40, 45, 61, 76, 88, 97 17, 42, 60, 66, 95, 113, 138, 148 vccint (5.0 v only) 3, 43 39,91 41, 93 61, 143 vccio (3.3 v or 5.0 v) 13, 26, 38, 53, 66, 78 3, 18, 34, 51, 66, 82 5, 20, 36, 53, 68, 84 8, 26, 55, 79, 104, 133 no connect (n.c.) 6, 39, 46, 79 1, 2, 3, 4, 5, 6, 34, 35, 36, 37, 38, 39, 40, 45, 46, 47, 74, 75, 76, 81, 82, 83, 84, 85, 86, 87, 115, 116, 117, 118, 119, 120, 124, 125, 126, 127, 154, 155, 156, 157 total user i/o pins (5) 60 80 80 100 altera corporation 67 max 7000 pr ogrammab le logic de vice f amil y data sheet table 47. epm7160e & epm7160s i/o pin-outs (part 1 of 3) lab mc 84-pin plcc 100-pin tqf p (1) , (2) 100-pin pqfp (3) 160-pin pqfp lab mc 84-pin plcc 100-pin tqfp (1) , (2) 100-pin pqfp (3) 160-pin pqfp a 1 11 100 2 158 c 33 19 21 27 2 34 3 10 99 1 153 35 25 17 19 25 4 36 5 152 37 24 6 98 100 151 38 24 16 18 23 7 39 8 9 97 99 150 40 23 (4) 15 (4) 17 (4) 22 (4) 9 8 96 98 149 41 10 12 16 10 42 11 5 94 96 147 43 20 12 14 18 12 44 13 146 45 19 14 93 95 145 46 21 13 15 20 15 47 16 4 92 94 144 48 22 14 16 21 b 17 18 9 11 15 d 49 48 18 50 19 17 8 10 14 51 33 28 30 44 20 52 21 13 53 27 29 43 22 7 9 12 54 31 25 27 41 23 55 24 16 6 8 11 56 30 24 26 33 25 15 5 7 10 57 32 26 58 27 14 (4) 4 (4) 6 (4) 9 (4) 59 29 23 25 31 28 60 29 7 61 22 24 30 30 2 4 160 62 28 21 23 29 31 63 32 12 1 3 159 64 27 20 22 28 68 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet e 65 59 g 97 73 66 98 67 41 37 39 58 99 52 49 51 77 68 100 69 36 38 57 101 50 52 78 70 40 35 37 56 102 54 52 54 80 71 103 72 37 33 35 54 104 55 53 55 88 73 53 105 89 74 106 75 36 32 34 52 107 56 54 56 90 76 108 77 31 33 51 109 55 57 91 78 35 30 32 50 110 57 56 58 92 79 111 80 34 29 31 49 112 58 57 59 93 f 81 62 h 113 58 60 94 82 114 83 44 40 42 63 115 60 60 62 96 84 116 85 41 43 64 117 97 86 45 42 44 65 118 61 61 63 98 87 119 88 48 44 46 67 120 62 (4) 62 (4) 64 (4) 99 (4) 89 68 121 67 69 105 90 122 91 49 45 47 69 123 65 65 67 103 92 124 93 46 48 70 125 102 94 50 47 49 71 126 64 64 66 101 95 127 96 51 48 50 72 128 63 63 65 100 table 47. epm7160e & epm7160s i/o pin-outs (part 2 of 3) lab mc 84-pin plcc 100-pin tqf p (1) , (2) 100-pin pqfp (3) 160-pin pqfp lab mc 84-pin plcc 100-pin tqfp (1) , (2) 100-pin pqfp (3) 160-pin pqfp altera corporation 69 max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) epm7160e devices are not available in the 100-pin tqfp package. (2) a complete thermal analysis should be performed before committing a design to this device package. (3) epm7160s devices are not available in the 100-pin pqfp package. (4) this jtag pin applies to max 7000s devices only and this pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for bst or with isp, this pin is not available as a user i/o pin. (5) the user i/o pin count includes dedicated input pins and all i/o pins. i 129 67 68 70 106 j 145 74 77 79 123 130 146 131 68 69 71 107 147 75 78 80 128 132 148 133 108 149 129 134 70 72 109 150 79 81 130 135 151 136 69 71 73 110 152 76 80 82 131 137 70 72 74 111 153 77 81 83 132 138 154 139 71 (4) 73 (4) 75 (4) 112 (4) 155 80 83 85 134 140 156 141 114 157 135 142 75 77 121 158 84 86 136 143 159 144 73 76 78 122 160 81 85 87 137 table 47. epm7160e & epm7160s i/o pin-outs (part 3 of 3) lab mc 84-pin plcc 100-pin tqf p (1) , (2) 100-pin pqfp (3) 160-pin pqfp lab mc 84-pin plcc 100-pin tqfp (1) , (2) 100-pin pqfp (3) 160-pin pqfp 70 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 48. epm7192e & epm7192s dedicated pin-outs dedicated pin 160-pin pga (1) 160-pin pqfp input / gclk1 m8 139 input / gclrn n8 141 input / oe1 p8 140 input / oe2 / gclk2 r8 142 tdi (2) p9 146 tms (2) g15 23 tck (2) g2 98 tdo (2) r7 135 gnd c4, c6, c11, d7, d9, d13, g4, h12, j4, m7, m9, m13, n4, n11 3, 18, 32, 47, 57, 64, 66, 81, 96, 111, 126, 138, 143, 148 vccint (5.0 v on ly) c7, c9, n7, n9 56, 65, 137, 144 vccio (3.3 v or 5.0 v) c5, c10, c12, d3, g12, h4, j12, m3, n5, n12 10, 25, 40, 55, 74, 89, 103, 118, 133, 155 no connect (n.c.) a1, a2, a14, a15, r1, r2, r14, r15 1, 11, 39,54, 67, 82, 110, 120 total user i/o pins (3) 120 120 table 49. epm7192e & epm7192s i/o pin-outs (part 1 of 3) lab mc 160-pin pga (1) 160-pin pqfp lab mc 160-pin pga (1) 160-pin pqfp lab mc 160-pin pga (1) 160-pin pqfp a 1 m12 156 b 17 l14 8 c 33 h14 21 2 18 34 3 p11 154 19 m14 7 35 j13 20 4 20 36 5 p12 153 21 m15 6 37 h15 19 6 p10 152 22 n14 5 38 j15 17 7 23 39 8 r12 151 24 n15 4 40 j14 16 9 n10 150 25 p15 2 41 k15 15 10 26 42 11 r11 149 27 n13 160 43 k13 14 12 28 44 13 r10 147 29 p14 159 45 l15 13 14 p9 (2) 146 (2) 30 p13 158 46 k14 12 15 31 47 16 r9 145 32 r13 157 48 l13 9 altera corporation 71 max 7000 pr ogrammab le logic de vice f amil y data sheet d 49 d15 33 f 81 d8 60 h 113 a3 76 50 82 114 51 e15 31 83 a9 59 115 b4 77 52 84 116 53 e14 30 85 c8 58 117 b3 78 54 f15 29 86 b9 53 118 c3 79 55 87 119 56 f13 28 88 a10 52 120 b2 80 57 g14 27 89 b10 51 121 b1 83 58 90 122 59 f14 26 91 a11 50 123 c2 84 60 92 124 61 g13 24 93 b11 49 125 c1 85 62 g15 (2) 23 (2) 94 a12 48 126 d2 86 63 95 127 64 h13 22 96 a13 46 128 d1 87 e 65 b12 45 g 97 a8 61 i 129 e3 88 66 98 130 67 b13 44 99 b8 62 131 f3 90 68 100 132 69 c13 43 101 a7 63 133 e2 91 70 b14 42 102 a6 68 134 f2 92 71 103 135 72 c14 41 104 b7 69 136 e1 93 73 d12 38 105 a5 70 137 g3 94 74 106 138 75 b15 37 107 b6 71 139 f1 95 76 108 140 77 d14 36 109 a4 72 141 g1 97 78 c15 35 110 b5 73 142 g2 (2) 98 (2) 79 111 143 80 e13 34 112 d4 75 144 h1 99 table 49. epm7192e & epm7192s i/o pin-outs (part 2 of 3) lab mc 160-pin pga (1) 160-pin pqfp lab mc 160-pin pga (1) 160-pin pqfp lab mc 160-pin pga (1) 160-pin pqfp 72 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) epm7192s devices are not available in the 160-pin pga pa ckage . (2) this jtag pin applies to m ax 7000s devices only and t his pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for isp, this pin is not available as a user i/o pin . (3) the user i/o pin count includes dedicated input pins and all i/o pins. j 145 h2 100 k 161 l2 113 l 177 r3 125 146 162 178 147 j1 101 163 n1 114 179 r4 127 148 164 180 149 h3 102 165 l3 115 181 m4 128 150 j3 104 166 p1 116 182 r5 129 151 167 183 152 k1 105 168 m2 117 184 p5 130 153 j2 106 169 n2 119 185 r6 131 154 170 186 155 k2 107 171 p2 121 187 p6 132 156 172 188 157 k3 108 173 n3 122 189 n6 134 158 l1 109 174 p3 123 190 r7 (2) 135 (2) 159 175 191 160 m1 112 176 p4 124 192 p7 136 table 49. epm7192e & epm7192s i/o pin-outs (part 3 of 3) lab mc 160-pin pga (1) 160-pin pqfp lab mc 160-pin pga (1) 160-pin pqfp lab mc 160-pin pga (1) 160-pin pqfp altera corporation 73 max 7000 pr ogrammab le logic de vice f amil y data sheet table 50. epm7256e & epm7256s dedicated pin-outs dedicated pin 160-pin pqfp (1) , (2) 192-pin pga (2) 208-pin rqfp/pqfp (3) input / gclk1 139 p9 184 input / gclrn 141 r9 182 input / oe1 140 t9 183 input / oe2 / gclk2 142 u9 181 tdi (4) 146 u10 176 tms (4) 23 h15 127 tck (4) 98 h3 30 tdo (4) 135 u8 189 gnd 3, 18, 32, 47, 57, 64, 66, 81, 96, 111, 126, 138, 143, 148 c7, c13, d4, d8, d10, g14, h4, k14, l4, p8, p10, p15, r4, r11 14, 32, 50, 72, 75, 82, 94, 116, 134, 152, 174, 180, 185, 200 vccint (5.0 v only) 56, 65, 137, 144 d7, d11, p7, p11 74, 83, 179, 186 vccio (3.3 v or 5.0 v) 10, 25, 40, 55, 74, 89, 103, 118, 133, 155 c5, c11, d14, g4, h14, k4, l14, p3, r5, r14 5, 23, 41, 63, 85, 107, 125, 143, 165, 191 no connect (n.c.) 1, 2, 51, 52, 53, 54, 103, 104, 105, 106, 155, 156, 157, 158, 207, 208. total user i/o pins (5) 128 160 160 74 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet table 51. epm7256e & epm7256s i/o pin-outs (part 1 of 5) lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp (3) a 1 2 u17 153 c 33 39 b17 108 2 34 3 1 r16 154 35 38 c15 109 4 36 5 160 p14 159 37 37 c17 110 6 u16 160 38 c16 111 7 39 8 159 r15 161 40 36 d17 112 9 158 u15 162 41 35 d15 113 10 42 11 157 t15 163 43 34 e17 114 12 44 13 156 u14 164 45 33 d16 115 14 u13 166 46 e15 117 15 47 16 154 t14 167 48 31 f16 118 b 17 12 n17 141 d 49 49 a14 92 18 50 19 11 m16 142 51 48 b12 93 20 52 21 9 m15 144 53 46 b13 95 22 p17 145 54 a15 96 23 55 24 8 n16 146 56 45 b14 97 25 7 r17 147 57 44 a16 98 26 58 27 6 p16 148 59 43 c14 99 28 60 29 5 t17 149 61 42 b16 100 30 n15 150 62 b15 101 31 63 32 4 t16 151 64 41 a17 102 altera corporation 75 max 7000 pr ogrammab le logic de vice f amil y data sheet e 65 153 u12 168 g 97 30 e16 119 66 98 67 152 r13 169 99 29 f17 120 68 100 69 151 u11 170 101 28 f15 121 70 t13 171 102 g16 122 71 103 72 150 t11 172 104 27 g15 123 73 149 t12 173 105 26 g17 124 74 106 75 147 r12 175 107 24 h17 126 76 108 77 146 (4) u10 (4) 176 (4) 109 23 (4) h15 (4) 127 (4) 78 r10 177 110 j17 128 79 111 80 145 t10 178 112 22 h16 129 f 81 21 j16 130 h 113 60 c9 79 82 114 83 20 j15 131 115 59 d9 80 84 116 85 19 k17 132 117 58 c10 81 86 j14 133 118 a10 84 87 119 88 17 k16 135 120 54 a11 86 89 16 k15 136 121 53 b10 87 90 122 91 15 l17 137 123 52 a12 88 92 124 93 14 l16 138 125 51 b11 89 94 m17 139 126 a13 90 95 127 96 13 l15 140 128 50 c12 91 table 51. epm7256e & epm7256s i/o pin-outs (part 2 of 5) lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp (3) 76 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet i 129 128 u6 197 j 145 100 j2 27 130 146 131 129 t5 196 147 101 j3 26 132 148 133 130 u7 195 149 102 k1 25 134 t6 194 150 j4 24 135 151 136 131 t7 193 152 104 k2 22 137 132 r6 192 153 105 k3 21 138 154 139 134 r7 190 155 106 l1 20 140 156 141 135 (4) u8 (4) 189 (4) 157 107 l2 19 142 r8 188 158 m1 18 143 159 144 136 t8 187 160 108 l3 17 table 51. epm7256e & epm7256s i/o pin-outs (part 3 of 5) lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp (3) altera corporation 77 max 7000 pr ogrammab le logic de vice f amil y data sheet k 161 91 f3 38 m 193 119 u1 4 162 194 163 92 f1 37 195 120 r2 3 164 196 165 93 e2 36 197 121 r3 206 166 g2 35 198 u2 205 167 199 168 94 g3 34 200 122 p4 204 169 95 g1 33 201 123 u3 203 170 202 171 97 h1 31 203 124 t3 202 172 204 173 98 (4) h3 (4) 30 (4) 205 125 u4 201 174 j1 29 206 u5 199 175 207 176 99 h2 28 208 127 t4 198 l 177 61 b9 78 n 209 109 n1 16 178 210 179 62 c8 77 211 110 m2 15 180 212 181 63 a9 76 213 112 m3 13 182 a8 73 214 p1 12 183 215 184 67 a7 71 216 113 n2 11 185 68 b8 70 217 114 r1 10 186 218 187 69 a6 69 219 115 p2 9 188 220 189 70 b7 68 221 116 t1 8 190 a5 67 222 n3 7 191 223 192 71 c6 66 224 117 t2 6 table 51. epm7256e & epm7256s i/o pin-outs (part 4 of 5) lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp (3) 78 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet notes to tables: (1) a complete thermal analysis should be performed before committing a design to this device package. see the operating requirements for altera devices data sheet for more information. (2) epm7256s devices is not available in the 160-pin pqfp package. (3) epm7256e devices are not available in the 208-pin rqfp/pqfp packages. (4) this jtag pin applies to m ax 7000s devices only and t his pin may function as either a jtag port or a user i/o pin. if the device is configured to use the jtag ports for isp, this pin is not available as a user i/o pin. (5) the user i/o pin count includes dedicated input pins and all i/o pins. o 225 82 b1 49 p 241 72 a4 65 226 242 227 83 c3 48 243 73 b6 64 228 244 229 84 c1 47 245 75 b5 62 230 d3 46 246 a3 61 231 247 232 85 d1 45 248 76 b4 60 233 86 c2 44 249 77 a2 59 234 250 235 87 e1 43 251 78 c4 58 236 252 237 88 e3 42 253 79 b2 57 238 d2 40 254 b3 56 239 255 240 90 f2 39 256 80 a1 55 table 51. epm7256e & epm7256s i/o pin-outs (part 5 of 5) lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp lab mc 160-pin pqfp (1) , (2) 192-pin pg a (2) 208-pin rqfp/pqfp (3) altera corporation 79 max 7000 pr ogrammab le logic de vice f amil y data sheet figures 16 through 22 show the package pin-out diagrams for max 7000 devices. figure 16. 44-pin package pin-out diagram package outlines not drawn to scale. pin functions shown in parentheses are for max 7000s or max 7000e devices only . notes: (1) these pins are available in max 7000e and max 7000s devices only. (2) jtag ports are a vailable in max 7000s devices only . 4 4 - p i n p l c c i / o i / o i / o v c c i n p u t / o e 2 / ( g c l k 2 ) ( 1 ) i n p u t / g c l r n i n p u t / o e 1 n i n p u t / g c l k 1 g n d i / o i / o i / o i / o / ( t d o ) ( 2 ) i / o i / o v c c i / o i / o i / o / ( t c k ) ( 2 ) i / o g n d i / o i / o i / o i / o i / o g n d v c c i / o i / o i / o i / o i / o 6 5 4 3 2 1 4 4 4 3 4 2 4 1 4 0 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 e p m 7 0 3 2 e p m 7 0 3 2 s e p m 7 0 6 4 e p m 7 0 6 4 s ( 2 ) i / o / ( t d i ) i / o i / o g n d i / o i / o ( 2 ) i / o / ( t m s ) i / o v c c i / o i / o 4 4 - p i n p q f p p i n 1 2 p i n 2 3 p i n 3 4 p i n 1 i / o i / o i / o v c c i n p u t / o e 2 / ( g c l k 2 ) ( 1 ) i n p u t / g c l r n i n p u t / o e 1 n i n p u t / / g c l k 1 g n d i / o i / o i / o i / o / ( t d o ) ( 2 ) i / o i / o v c c i / o i / o i / o / ( t c k ) ( 2 ) i / o g n d i / o i / o i / o i / o i / o g n d v c c i / o i / o i / o i / o i / o i / o i / o g n d i / o i / o ( 2 ) i / o / ( t m s ) i / o v c c i / o i / o e p m 7 0 3 2 4 4 - p i n t q f p p i n 1 2 p i n 2 3 p i n 3 4 p i n 1 i / o i / o i / o v c c i n p u t / o e 2 / ( g c l k 2 ) ( 1 ) i n p u t / g c l r n i n p u t / o e 1 n i n p u t / g c l k 1 g n d i / o i / o i / o i / o / ( t d o ) ( 2 ) i / o i / o v c c i / o i / o i / o / ( t c k ) ( 2 ) i / o g n d i / o i / o i / o i / o i / o g n d v c c i / o i / o i / o i / o i / o ( 2 ) i / o / ( t d i ) i / o i / o g n d i / o i / o ( 2 ) i / o / ( t m s ) i / o v c c i / o i / o e p m 7 0 3 2 e p m 7 0 3 2 s e p m 7 0 6 4 e p m 7 0 6 4 s ( 2 ) i / o / ( t d i ) 80 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet figure 17. 68-pin package pin-out diagram package outlines not drawn to scale. pin functions shown in parentheses are for max 7000s or max 7000e devices only . notes: (1) these pins are available in max 7000e and max 7000s devices only. (2) jtag ports are available in max 7000s devices only. 6 8 - p i n p l c c e p m 7 0 6 4 e p m 7 0 9 6 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 9 8 7 6 5 4 3 2 1 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 i / o i / o g n d i / o / ( t d o ) ( 2 ) i / o i / o i / o v c c i o i / o i / o i / o / ( t c k ) ( 2 ) i / o g n d i / o i / o i / o i / o i / o v c c i o ( 2 ) i / o / ( t d i ) i / o i / o i / o g n d i / o i / o ( 2 ) i / o / ( t m s ) i / o v c c i o i / o i / o i / o i / o g n d i / o i / o i / o g n d i / o i / o v c c i n t i n p u t / o e 2 / ( g c l k 2 ) ( 1 ) i n p u t / g c l r n i n p u t / o e 1 i n p u t / g c l k 1 g n d i / o i / o v c c i o i / o i / o i / o i / o i / o i / o v c c i o i / o i / o g n d v c c i n t i / o i / o g n d i / o i / o i / o i / o v c c i o altera corporation 81 max 7000 pr ogrammab le logic de vice f amil y data sheet figure 18. 84-pin package pin-out diagram package outline not drawn to scale. pin functions in parentheses are for max 7000s or max 7000e devices only . notes: (1) pins 6, 39, 46, and 79 are no-connect (n.c.) pins on epm7096, epm7160e, and epm7160s devices. (2) this pin is a vailable in max 7000e and max 7000s devices only. (3) jtag ports are a vailable in max 7000s devices only . 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 i / o v c c i o i / o / ( t d i ) ( 3 ) i / o i / o i / o i / o g n d i / o i / o i / o i / o / ( t m s ) ( 3 ) i / o i / o v c c i o i / o i / o i / o i / o i / o g n d i / o i / o i / o i / o g n d i / o ( 1 ) i / o i / o v c c i n t i n p u t / o e 2 / ( g c l k 2 ) ( 2 ) i n p u t / g l c r n i n p u t / o e 1 i n p u t / g c l k 1 g n d i / o i / o i / o ( 1 ) v c c i o i / o i / o i / o 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 1 1 0 9 8 7 6 5 4 3 2 1 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 i / o i / o g n d i / o / ( t d o ) ( 3 ) i / o i / o i / o i / o v c c i o i / o i / o i / o i / o / ( t c k ) ( 3 ) i / o i / o g n d i / o i / o i / o i / o i / o i / o i / o i / o i / o i / o v c c i o i / o ( 1 ) i / o i / o g n d v c c i n t i / o i / o i / o ( 1 ) g n d i / o i / o i / o i / o i / o v c c i o 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 e p m 7 0 6 4 e p m 7 0 6 4 s e p m 7 0 9 6 e p m 7 1 2 8 e e p m 7 1 2 8 s e p m 7 1 6 0 e e p m 7 1 6 0 s 8 4 - p i n p l c c 82 altera corporation max 7000 pr ogrammab le logic de vice f amil y data sheet figure 19. 100-pin package pin-out diagram package outline not drawn to scale. figure 20. 160-pin package pin-out diagram package outli ne not drawn to scale. 1 0 0 - p i n p q f p p i n 3 1 e p m 7 0 6 4 e p m 7 0 9 6 e p m 7 1 2 8 e e p m 7 1 2 8 s e p m 7 1 6 0 e p i n 8 1 p i n 1 p i n 5 1 1 0 0 - p i n t q f p p i n 1 p i n 2 6 p i n 7 6 p i n 5 1 e p m 7 0 6 4 s e p m 7 1 2 8 s e p m 7 1 6 0 s pin 1 epm7128e epm7128s epm7160e epm7160s epm7192e epm7192s epm7256e pin 121 pin 81 pin 41 160-pin pga 160-pin pqfp r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 epm7192e bottom v ie w altera corporation 83 max 7000 pr ogrammab le logic de vice f amil y data sheet figure 21. 192-pin package pin-out diagram package outline not drawn to scale. figure 22. 208-pin package pin-out diagram package outline not drawn to scale. 192-pin pga epm7256e bottom v ie w u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 208-pin pqfp/rqfp pin 1 pin 157 pin 105 pin 53 epm7256e epm7256s 84 altera corporation max 7000 programmable logic device family data sheet revision history the information contained in the max 7000 programmable logic device family data sheet version 6.01 supersedes information published in previous version. the following changes were made to the max 7000 programmable logic device family data sheet version 6.01: n the masterblaster serial/usb download cable was added to this document n figures 3 and 4 were updated. n t cppw timing parameter information was clarified in the timing model ?section. copyright ? 1995, 1996, 1997, 1998 , 1 9 9 9 altera corporation, 101 innovation drive, san jose, c a 95134, usa, all rights r eserved. by accessing this information, you ag r ee to be bound by the terms of alteras legal notice. |
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